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master
constantinfuerst 3 years ago
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131c3255a2
  1. 2
      .gitattributes
  2. 33
      .gitignore
  3. 36
      LICENSE.md
  4. 2
      README.md
  5. 31
      cpu_design_and_emulator.sln
  6. 71
      cpu_design_and_emulator/bus/bus.cpp
  7. 38
      cpu_design_and_emulator/bus/bus.h
  8. 191
      cpu_design_and_emulator/cpu_design_and_emulator.vcxproj
  9. 66
      cpu_design_and_emulator/cpu_design_and_emulator.vcxproj.filters
  10. 6
      cpu_design_and_emulator/cpu_design_and_emulator.vcxproj.user
  11. 1
      cpu_design_and_emulator/main.cpp
  12. 57
      cpu_design_and_emulator/microprocessor/cpu/addressing_modes.cpp
  13. 305
      cpu_design_and_emulator/microprocessor/cpu/cpu.cpp
  14. 72
      cpu_design_and_emulator/microprocessor/cpu/cpu.h
  15. BIN
      cpu_design_and_emulator/microprocessor/cpu/customCPU-INSTR.xlsx
  16. 266
      cpu_design_and_emulator/microprocessor/cpu/instructions.cpp
  17. 3
      cpu_design_and_emulator/microprocessor/input/input_handler.cpp
  18. 3
      cpu_design_and_emulator/microprocessor/input/input_handler.h
  19. 14
      cpu_design_and_emulator/microprocessor/microprocessor.cpp
  20. 17
      cpu_design_and_emulator/microprocessor/microprocessor.h
  21. 2
      cpu_design_and_emulator/microprocessor/output/output_processor.cpp
  22. 2
      cpu_design_and_emulator/microprocessor/output/output_processor.h
  23. 1
      cpu_design_and_emulator/pch.cpp
  24. 5
      cpu_design_and_emulator/pch.h

2
.gitattributes

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# Auto detect text files and perform LF normalization
* text=auto

33
.gitignore

@ -0,0 +1,33 @@
*.ipch
*.db
*.suo
*.obj
*.tlog
*.log
*.pch
*.codeanalysisast
*.idb
*.pdb
*.lastcodeanalysissucceeded
*.iobj
*.ipdb
*.opendb
*.ilk
*.nupkg
*.targets
*.p7s
*.hpp
*.enc
*.sqlite
*.json
*.xml
*.ttf
packages/*
*.csg
*.zip
build/*
chessgame/chessgame.rc
chessgame/chessgame.aps
chessgame/icon.png
chessgame/resource.h

36
LICENSE.md

@ -0,0 +1,36 @@
PROGRAMM METADATA:
name: cpu design and emulator
copyright: (c) 2019 Constantin Fürst constantin@fuersten.info
LICENSE:
This work is created by Constantin Fürst.
If you are unsure if your use of this project is permitted or you'd like to use it in a way prohibited by the following license, please message "constantin@fuersten.info".
This work is licensed under the
Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
To view a copy of this license, visit https://creativecommons.org/licenses/by-nc-nd/4.0/ or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.
DISCLAIMER:
THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS 'AS IS' AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
SUCH DAMAGE.
IMAGE SOURCES:
I do not claim ownership of any of the assets in this library.
If you have a legitimate claim and would like me to remove them from here please message "constantin@fuersten.info" and I will remove them as quickly as possible.
The images were downloaded on the 21.3.2019 from the following Link:
https://doc-0s-0g-docs.googleusercontent.com/docs/securesc/ha0ro937gcuc7l7deffksulhg5h7mbp1/ccq7oldr1i4pa8jinjrimban5ngn4boh/1553198400000/16989609535124341763/*/1naW_v6WAWYPgCIWNDskxtBsM84FoaOLh?e=download
Which was discovered in the following youtube video:
https://www.youtube.com/watch?v=_4EuZI8Q8cs

2
README.md

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# cpu_design_and_emulator

31
cpu_design_and_emulator.sln

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Microsoft Visual Studio Solution File, Format Version 12.00
# Visual Studio Version 16
VisualStudioVersion = 16.0.29424.173
MinimumVisualStudioVersion = 10.0.40219.1
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "cpu_design_and_emulator", "cpu_design_and_emulator\cpu_design_and_emulator.vcxproj", "{3457606D-A726-4782-BA1A-B3509DEBD8C2}"
EndProject
Global
GlobalSection(SolutionConfigurationPlatforms) = preSolution
Debug|x64 = Debug|x64
Debug|x86 = Debug|x86
Release|x64 = Release|x64
Release|x86 = Release|x86
EndGlobalSection
GlobalSection(ProjectConfigurationPlatforms) = postSolution
{3457606D-A726-4782-BA1A-B3509DEBD8C2}.Debug|x64.ActiveCfg = Debug|x64
{3457606D-A726-4782-BA1A-B3509DEBD8C2}.Debug|x64.Build.0 = Debug|x64
{3457606D-A726-4782-BA1A-B3509DEBD8C2}.Debug|x86.ActiveCfg = Debug|Win32
{3457606D-A726-4782-BA1A-B3509DEBD8C2}.Debug|x86.Build.0 = Debug|Win32
{3457606D-A726-4782-BA1A-B3509DEBD8C2}.Release|x64.ActiveCfg = Release|x64
{3457606D-A726-4782-BA1A-B3509DEBD8C2}.Release|x64.Build.0 = Release|x64
{3457606D-A726-4782-BA1A-B3509DEBD8C2}.Release|x86.ActiveCfg = Release|Win32
{3457606D-A726-4782-BA1A-B3509DEBD8C2}.Release|x86.Build.0 = Release|Win32
EndGlobalSection
GlobalSection(SolutionProperties) = preSolution
HideSolutionNode = FALSE
EndGlobalSection
GlobalSection(ExtensibilityGlobals) = postSolution
SolutionGuid = {5E1312F5-B078-42D8-A1A8-DFC2620323AF}
EndGlobalSection
EndGlobal

71
cpu_design_and_emulator/bus/bus.cpp

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#include "pch.h"
#include "bus.h"
bool addressRange::inRange(const uint16_t& address) const{
if (address >= addrRangeLow && address <= addrRangeHigh)
return true;
return false;
}
bool addressRange::inRange(const addressRange& range) const {
if (inRange(range.addrRangeLow) || inRange(range.addrRangeHigh))
return true;
return false;
}
const addressRange& buselement::getRange() const {
return m_range;
}
addressRange::addressRange(const uint16_t& low, const uint16_t& high) {
readOnly = false;
noRead = false;
addrRangeLow = low;
addrRangeHigh = high;
}
addressRange::addressRange(const uint16_t& low, const uint16_t& high, bool readOnly_in) {
readOnly = readOnly_in;
noRead = false;
addrRangeLow = low;
addrRangeHigh = high;
}
addressRange::addressRange() {
readOnly = true;
noRead = true;
addrRangeLow = 0x0000;
addrRangeHigh = 0x0000;
}
bool bus::rangeFree(const addressRange& address) {
for (auto& element : m_connectedElements) {
if (element->getRange().inRange(address))
return false;
}
return true;
}
bool bus::attachElement(buselement* newElement) {
//check if the requested address range is already in use
if (!rangeFree(newElement->getRange()))
return false;
m_connectedElements.push_back(newElement);
return true;
}
uint8_t bus::read(const uint16_t& address) {
for (auto& element : m_connectedElements) {
if (element->getRange().inRange(address))
return element->read(address);
}
return 0x0000;
}
void bus::write(const uint16_t& address, const uint8_t& value) {
for (auto& element : m_connectedElements) {
if (element->getRange().inRange(address))
element->write(address, value);
}
}

38
cpu_design_and_emulator/bus/bus.h

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#pragma once
#include "pch.h"
struct addressRange {
bool readOnly;
bool noRead;
uint16_t addrRangeLow;
uint16_t addrRangeHigh;
[[nodiscard]] bool inRange(const uint16_t& address) const;
[[nodiscard]] bool inRange(const addressRange& range) const;
addressRange(const uint16_t& low, const uint16_t& high);
addressRange(const uint16_t& low, const uint16_t& high, bool readOnly_in);
addressRange();
};
class buselement {
private:
addressRange m_range;
public:
[[nodiscard]] const addressRange& getRange() const;
virtual void write(const uint16_t& address, const uint8_t& value) = 0;
virtual uint8_t read(const uint16_t& address) = 0;
buselement() = default;
};
class bus {
private:
std::vector<buselement*> m_connectedElements;
public:
bool rangeFree(const addressRange& range);
bool attachElement(buselement* newElement);
void write(const uint16_t& address, const uint8_t& value);
uint8_t read(const uint16_t& address);
};

191
cpu_design_and_emulator/cpu_design_and_emulator.vcxproj

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<ClCompile>
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1
cpu_design_and_emulator/main.cpp

@ -0,0 +1 @@
#include "pch.h"

57
cpu_design_and_emulator/microprocessor/cpu/addressing_modes.cpp

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#include "pch.h"
#include "cpu.h"
void cpu::IMP() {
m_addrAbs = 0x0000;
m_pc++;
}
void cpu::ZP0() {
m_addrAbs = read(m_pc);
m_addrAbs &= 0x00FF;
m_pc++;
}
void cpu::ABS() {
const uint16_t lo = read(m_pc);
m_pc++;
const uint16_t hi = read(m_pc) << 8;
m_pc++;
m_addrAbs = hi | lo;
}
void cpu::VAL() {
m_addrAbs = m_pc++;
}
void cpu::REL() {
m_addrRel = read(m_pc);
m_pc++;
if (m_addrRel & 0x80)
m_addrRel |= 0xFF00;
}
void cpu::DAV() {
const uint16_t lo = read(m_pc);
m_pc++;
const uint16_t hi = read(m_pc) << 8;
m_pc++;
m_addrAbs = hi | lo;
m_regTemp = read(m_pc);
m_pc++;
}
void cpu::DRV() {
m_addrRel = read(m_pc);
m_pc++;
if (m_addrRel & 0x80)
m_addrRel |= 0xFF00;
m_regTemp = read(m_pc);
m_pc++;
m_addrAbs = m_pc + m_addrRel;
}
void cpu::RTA() {
m_addrAbs = m_regGP[0];
m_addrAbs = m_regGP[1] << 8;
}

305
cpu_design_and_emulator/microprocessor/cpu/cpu.cpp

@ -0,0 +1,305 @@
#include "pch.h"
#include "cpu.h"
void cpu::onCycle() {
}
bool cpu::getStatus(statusFlag flag) {
return ((m_regStat & flag) > 0) ? 1 : 0;
}
void cpu::setStatus(statusFlag flag, bool value) {
if (value)
m_regStat |= flag;
else
m_regStat &= ~flag;
}
void cpu::readInstruction() {
opcode = read(m_pc);
m_pc++;
}
cpu::instruction::instruction(uint8_t oc, void ( cpu::* op)(), void ( cpu::* ad)()) {
opcode = oc;
operand = op;
loader = ad;
}
cpu::cpu() {
lookupTable = {
instruction(0x00, &cpu::IMP, &cpu::NOP),
instruction(0x01, &cpu::IMP, &cpu::NOP),
instruction(0x02, &cpu::IMP, &cpu::NOP),
instruction(0x03, &cpu::IMP, &cpu::NOP),
instruction(0x04, &cpu::IMP, &cpu::NOP),
instruction(0x05, &cpu::IMP, &cpu::NOP),
instruction(0x06, &cpu::IMP, &cpu::NOP),
instruction(0x07, &cpu::IMP, &cpu::NOP),
instruction(0x08, &cpu::IMP, &cpu::NOP),
instruction(0x09, &cpu::IMP, &cpu::NOP),
instruction(0x0a, &cpu::IMP, &cpu::NOP),
instruction(0x0b, &cpu::IMP, &cpu::NOP),
instruction(0x0c, &cpu::IMP, &cpu::NOP),
instruction(0x0d, &cpu::IMP, &cpu::NOP),
instruction(0x0e, &cpu::IMP, &cpu::NOP),
instruction(0x0f, &cpu::IMP, &cpu::NOP),
instruction(0x10, &cpu::IMP, &cpu::NOP),
instruction(0x11, &cpu::IMP, &cpu::NOP),
instruction(0x12, &cpu::IMP, &cpu::NOP),
instruction(0x13, &cpu::IMP, &cpu::NOP),
instruction(0x14, &cpu::IMP, &cpu::NOP),
instruction(0x15, &cpu::IMP, &cpu::NOP),
instruction(0x16, &cpu::IMP, &cpu::NOP),
instruction(0x17, &cpu::IMP, &cpu::NOP),
instruction(0x18, &cpu::IMP, &cpu::NOP),
instruction(0x19, &cpu::IMP, &cpu::NOP),
instruction(0x1a, &cpu::IMP, &cpu::NOP),
instruction(0x1b, &cpu::IMP, &cpu::NOP),
instruction(0x1c, &cpu::IMP, &cpu::NOP),
instruction(0x1d, &cpu::IMP, &cpu::NOP),
instruction(0x1e, &cpu::IMP, &cpu::NOP),
instruction(0x1f, &cpu::IMP, &cpu::NOP),
instruction(0x20, &cpu::IMP, &cpu::NOP),
instruction(0x21, &cpu::IMP, &cpu::NOP),
instruction(0x22, &cpu::IMP, &cpu::NOP),
instruction(0x23, &cpu::IMP, &cpu::NOP),
instruction(0x24, &cpu::IMP, &cpu::NOP),
instruction(0x25, &cpu::IMP, &cpu::NOP),
instruction(0x26, &cpu::IMP, &cpu::NOP),
instruction(0x27, &cpu::IMP, &cpu::NOP),
instruction(0x28, &cpu::IMP, &cpu::NOP),
instruction(0x29, &cpu::IMP, &cpu::NOP),
instruction(0x2a, &cpu::IMP, &cpu::NOP),
instruction(0x2b, &cpu::IMP, &cpu::NOP),
instruction(0x2c, &cpu::IMP, &cpu::NOP),
instruction(0x2d, &cpu::IMP, &cpu::NOP),
instruction(0x2e, &cpu::IMP, &cpu::NOP),
instruction(0x2f, &cpu::IMP, &cpu::NOP),
instruction(0x30, &cpu::IMP, &cpu::NOP),
instruction(0x31, &cpu::IMP, &cpu::NOP),
instruction(0x32, &cpu::IMP, &cpu::NOP),
instruction(0x33, &cpu::IMP, &cpu::NOP),
instruction(0x34, &cpu::IMP, &cpu::NOP),
instruction(0x35, &cpu::IMP, &cpu::NOP),
instruction(0x36, &cpu::IMP, &cpu::NOP),
instruction(0x37, &cpu::IMP, &cpu::NOP),
instruction(0x38, &cpu::IMP, &cpu::NOP),
instruction(0x39, &cpu::IMP, &cpu::NOP),
instruction(0x3a, &cpu::IMP, &cpu::NOP),
instruction(0x3b, &cpu::IMP, &cpu::NOP),
instruction(0x3c, &cpu::IMP, &cpu::NOP),
instruction(0x3d, &cpu::IMP, &cpu::NOP),
instruction(0x3e, &cpu::IMP, &cpu::NOP),
instruction(0x3f, &cpu::IMP, &cpu::NOP),
instruction(0x40, &cpu::IMP, &cpu::NOP),
instruction(0x41, &cpu::IMP, &cpu::NOP),
instruction(0x42, &cpu::IMP, &cpu::NOP),
instruction(0x43, &cpu::IMP, &cpu::NOP),
instruction(0x44, &cpu::IMP, &cpu::NOP),
instruction(0x45, &cpu::IMP, &cpu::NOP),
instruction(0x46, &cpu::IMP, &cpu::NOP),
instruction(0x47, &cpu::IMP, &cpu::NOP),
instruction(0x48, &cpu::IMP, &cpu::NOP),
instruction(0x49, &cpu::IMP, &cpu::NOP),
instruction(0x4a, &cpu::IMP, &cpu::NOP),
instruction(0x4b, &cpu::IMP, &cpu::NOP),
instruction(0x4c, &cpu::IMP, &cpu::NOP),
instruction(0x4d, &cpu::IMP, &cpu::NOP),
instruction(0x4e, &cpu::IMP, &cpu::NOP),
instruction(0x4f, &cpu::IMP, &cpu::NOP),
instruction(0x50, &cpu::IMP, &cpu::NOP),
instruction(0x51, &cpu::IMP, &cpu::NOP),
instruction(0x52, &cpu::IMP, &cpu::NOP),
instruction(0x53, &cpu::IMP, &cpu::NOP),
instruction(0x54, &cpu::IMP, &cpu::NOP),
instruction(0x55, &cpu::IMP, &cpu::NOP),
instruction(0x56, &cpu::IMP, &cpu::NOP),
instruction(0x57, &cpu::IMP, &cpu::NOP),
instruction(0x58, &cpu::IMP, &cpu::NOP),
instruction(0x59, &cpu::IMP, &cpu::NOP),
instruction(0x5a, &cpu::IMP, &cpu::NOP),
instruction(0x5b, &cpu::IMP, &cpu::NOP),
instruction(0x5c, &cpu::IMP, &cpu::NOP),
instruction(0x5d, &cpu::IMP, &cpu::NOP),
instruction(0x5e, &cpu::IMP, &cpu::NOP),
instruction(0x5f, &cpu::IMP, &cpu::NOP),
instruction(0x60, &cpu::IMP, &cpu::NOP),
instruction(0x61, &cpu::IMP, &cpu::NOP),
instruction(0x62, &cpu::IMP, &cpu::NOP),
instruction(0x63, &cpu::IMP, &cpu::NOP),
instruction(0x64, &cpu::IMP, &cpu::NOP),
instruction(0x65, &cpu::IMP, &cpu::NOP),
instruction(0x66, &cpu::IMP, &cpu::NOP),
instruction(0x67, &cpu::IMP, &cpu::NOP),
instruction(0x68, &cpu::IMP, &cpu::NOP),
instruction(0x69, &cpu::IMP, &cpu::NOP),
instruction(0x6a, &cpu::IMP, &cpu::NOP),
instruction(0x6b, &cpu::IMP, &cpu::NOP),
instruction(0x6c, &cpu::IMP, &cpu::NOP),
instruction(0x6d, &cpu::IMP, &cpu::NOP),
instruction(0x6e, &cpu::IMP, &cpu::NOP),
instruction(0x6f, &cpu::IMP, &cpu::NOP),
instruction(0x70, &cpu::IMP, &cpu::NOP),
instruction(0x71, &cpu::IMP, &cpu::NOP),
instruction(0x72, &cpu::IMP, &cpu::NOP),
instruction(0x73, &cpu::IMP, &cpu::NOP),
instruction(0x74, &cpu::IMP, &cpu::NOP),
instruction(0x75, &cpu::IMP, &cpu::NOP),
instruction(0x76, &cpu::IMP, &cpu::NOP),
instruction(0x77, &cpu::IMP, &cpu::NOP),
instruction(0x78, &cpu::IMP, &cpu::NOP),
instruction(0x79, &cpu::IMP, &cpu::NOP),
instruction(0x7a, &cpu::IMP, &cpu::NOP),
instruction(0x7b, &cpu::IMP, &cpu::NOP),
instruction(0x7c, &cpu::IMP, &cpu::NOP),
instruction(0x7d, &cpu::IMP, &cpu::NOP),
instruction(0x7e, &cpu::IMP, &cpu::NOP),
instruction(0x7f, &cpu::IMP, &cpu::NOP),
instruction(0x80, &cpu::IMP, &cpu::NOP),
instruction(0x81, &cpu::IMP, &cpu::NOP),
instruction(0x82, &cpu::IMP, &cpu::NOP),
instruction(0x83, &cpu::IMP, &cpu::NOP),
instruction(0x84, &cpu::IMP, &cpu::NOP),
instruction(0x85, &cpu::IMP, &cpu::NOP),
instruction(0x86, &cpu::IMP, &cpu::NOP),
instruction(0x87, &cpu::IMP, &cpu::NOP),
instruction(0x88, &cpu::IMP, &cpu::NOP),
instruction(0x89, &cpu::IMP, &cpu::NOP),
instruction(0x8a, &cpu::IMP, &cpu::NOP),
instruction(0x8b, &cpu::IMP, &cpu::NOP),
instruction(0x8c, &cpu::IMP, &cpu::NOP),
instruction(0x8d, &cpu::IMP, &cpu::NOP),
instruction(0x8e, &cpu::IMP, &cpu::NOP),
instruction(0x8f, &cpu::IMP, &cpu::NOP),
instruction(0x90, &cpu::IMP, &cpu::NOP),
instruction(0x91, &cpu::IMP, &cpu::NOP),
instruction(0x92, &cpu::IMP, &cpu::NOP),
instruction(0x93, &cpu::IMP, &cpu::NOP),
instruction(0x94, &cpu::IMP, &cpu::NOP),
instruction(0x95, &cpu::IMP, &cpu::NOP),
instruction(0x96, &cpu::IMP, &cpu::NOP),
instruction(0x97, &cpu::IMP, &cpu::NOP),
instruction(0x98, &cpu::IMP, &cpu::NOP),
instruction(0x99, &cpu::IMP, &cpu::NOP),
instruction(0x9a, &cpu::IMP, &cpu::NOP),
instruction(0x9b, &cpu::IMP, &cpu::NOP),
instruction(0x9c, &cpu::IMP, &cpu::NOP),
instruction(0x9d, &cpu::IMP, &cpu::NOP),
instruction(0x9e, &cpu::IMP, &cpu::NOP),
instruction(0x9f, &cpu::IMP, &cpu::NOP),
instruction(0xa0, &cpu::IMP, &cpu::NOP),
instruction(0xa1, &cpu::IMP, &cpu::NOP),
instruction(0xa2, &cpu::IMP, &cpu::NOP),
instruction(0xa3, &cpu::IMP, &cpu::NOP),
instruction(0xa4, &cpu::IMP, &cpu::NOP),
instruction(0xa5, &cpu::IMP, &cpu::NOP),
instruction(0xa6, &cpu::IMP, &cpu::NOP),
instruction(0xa7, &cpu::IMP, &cpu::NOP),
instruction(0xa8, &cpu::IMP, &cpu::NOP),
instruction(0xa9, &cpu::IMP, &cpu::NOP),
instruction(0xaa, &cpu::IMP, &cpu::NOP),
instruction(0xab, &cpu::IMP, &cpu::NOP),
instruction(0xac, &cpu::IMP, &cpu::NOP),
instruction(0xad, &cpu::IMP, &cpu::NOP),
instruction(0xae, &cpu::IMP, &cpu::NOP),
instruction(0xaf, &cpu::IMP, &cpu::NOP),
instruction(0xb0, &cpu::IMP, &cpu::NOP),
instruction(0xb1, &cpu::IMP, &cpu::NOP),
instruction(0xb2, &cpu::IMP, &cpu::NOP),
instruction(0xb3, &cpu::IMP, &cpu::NOP),
instruction(0xb4, &cpu::IMP, &cpu::NOP),
instruction(0xb5, &cpu::IMP, &cpu::NOP),
instruction(0xb6, &cpu::IMP, &cpu::NOP),
instruction(0xb7, &cpu::IMP, &cpu::NOP),
instruction(0xb8, &cpu::IMP, &cpu::NOP),
instruction(0xb9, &cpu::IMP, &cpu::NOP),
instruction(0xba, &cpu::IMP, &cpu::NOP),
instruction(0xbb, &cpu::IMP, &cpu::NOP),
instruction(0xbc, &cpu::IMP, &cpu::NOP),
instruction(0xbd, &cpu::IMP, &cpu::NOP),
instruction(0xbe, &cpu::IMP, &cpu::NOP),
instruction(0xbf, &cpu::IMP, &cpu::NOP),
instruction(0xc0, &cpu::IMP, &cpu::NOP),
instruction(0xc1, &cpu::IMP, &cpu::NOP),
instruction(0xc2, &cpu::IMP, &cpu::NOP),
instruction(0xc3, &cpu::IMP, &cpu::NOP),
instruction(0xc4, &cpu::IMP, &cpu::NOP),
instruction(0xc5, &cpu::IMP, &cpu::NOP),
instruction(0xc6, &cpu::IMP, &cpu::NOP),
instruction(0xc7, &cpu::IMP, &cpu::NOP),
instruction(0xc8, &cpu::IMP, &cpu::NOP),
instruction(0xc9, &cpu::IMP, &cpu::NOP),
instruction(0xca, &cpu::IMP, &cpu::NOP),
instruction(0xcb, &cpu::IMP, &cpu::NOP),
instruction(0xcc, &cpu::IMP, &cpu::NOP),
instruction(0xcd, &cpu::IMP, &cpu::NOP),
instruction(0xce, &cpu::IMP, &cpu::NOP),
instruction(0xcf, &cpu::IMP, &cpu::NOP),
instruction(0xd0, &cpu::IMP, &cpu::NOP),
instruction(0xd1, &cpu::IMP, &cpu::NOP),
instruction(0xd2, &cpu::IMP, &cpu::NOP),
instruction(0xd3, &cpu::IMP, &cpu::NOP),
instruction(0xd4, &cpu::IMP, &cpu::NOP),
instruction(0xd5, &cpu::IMP, &cpu::NOP),
instruction(0xd6, &cpu::IMP, &cpu::NOP),
instruction(0xd7, &cpu::IMP, &cpu::NOP),
instruction(0xd8, &cpu::IMP, &cpu::NOP),
instruction(0xd9, &cpu::IMP, &cpu::NOP),
instruction(0xda, &cpu::IMP, &cpu::NOP),
instruction(0xdb, &cpu::IMP, &cpu::NOP),
instruction(0xdc, &cpu::IMP, &cpu::NOP),
instruction(0xdd, &cpu::IMP, &cpu::NOP),
instruction(0xde, &cpu::IMP, &cpu::NOP),
instruction(0xdf, &cpu::IMP, &cpu::NOP),
instruction(0xe0, &cpu::IMP, &cpu::NOP),
instruction(0xe1, &cpu::IMP, &cpu::NOP),
instruction(0xe2, &cpu::IMP, &cpu::NOP),
instruction(0xe3, &cpu::IMP, &cpu::NOP),
instruction(0xe4, &cpu::IMP, &cpu::NOP),
instruction(0xe5, &cpu::IMP, &cpu::NOP),
instruction(0xe6, &cpu::IMP, &cpu::NOP),
instruction(0xe7, &cpu::IMP, &cpu::NOP),
instruction(0xe8, &cpu::IMP, &cpu::NOP),
instruction(0xe9, &cpu::IMP, &cpu::NOP),
instruction(0xea, &cpu::IMP, &cpu::NOP),
instruction(0xeb, &cpu::IMP, &cpu::NOP),
instruction(0xec, &cpu::IMP, &cpu::NOP),
instruction(0xed, &cpu::IMP, &cpu::NOP),
instruction(0xee, &cpu::IMP, &cpu::NOP),
instruction(0xef, &cpu::IMP, &cpu::NOP),
instruction(0xf0, &cpu::IMP, &cpu::NOP),
instruction(0xf1, &cpu::IMP, &cpu::NOP),
instruction(0xf2, &cpu::IMP, &cpu::NOP),
instruction(0xf3, &cpu::IMP, &cpu::NOP),
instruction(0xf4, &cpu::IMP, &cpu::NOP),
instruction(0xf5, &cpu::IMP, &cpu::NOP),
instruction(0xf6, &cpu::IMP, &cpu::NOP),
instruction(0xf7, &cpu::IMP, &cpu::NOP),
instruction(0xf8, &cpu::IMP, &cpu::NOP),
instruction(0xf9, &cpu::IMP, &cpu::NOP),
instruction(0xfa, &cpu::IMP, &cpu::NOP),
instruction(0xfb, &cpu::IMP, &cpu::NOP),
instruction(0xfc, &cpu::IMP, &cpu::NOP),
instruction(0xfd, &cpu::IMP, &cpu::NOP),
instruction(0xfe, &cpu::IMP, &cpu::NOP),
instruction(0xff, &cpu::IMP, &cpu::NOP),
};
}

72
cpu_design_and_emulator/microprocessor/cpu/cpu.h

@ -0,0 +1,72 @@
#pragma once
#include "pch.h"
#include "../microprocessor.h"
class cpu final : microprocessor {
private:
uint8_t opcode = 0x00;
uint16_t m_pc = 0x0000;
uint16_t m_addrAbs = 0x0000;
uint16_t m_addrRel = 0x0000;
uint16_t m_regRet = 0x0000;
uint8_t m_regAcc = 0x00;
uint8_t m_regStat = 0x00;
uint8_t m_regTemp = 0x00;
std::array<uint8_t, 4> m_regGP = { 0x00 };
std::array<uint8_t, 2> m_regJoined = { 0x00 };
int cycles = 0;
enum statusFlag {
Negative = (1 << 0),
Overflow = (1 << 1),
TextOnly = (1 << 2),
Break = (1 << 3),
Decimal = (1 << 4),
Interrupt = (1 << 5),
Zero = (1 << 6),
Carry = (1 << 7),
N = (1 << 0),
V = (1 << 1),
T = (1 << 2),
B = (1 << 3),
D = (1 << 4),
I = (1 << 5),
Z = (1 << 6),
C = (1 << 7)
};
bool getStatus(statusFlag flag);
void setStatus(statusFlag flag, bool value);
//memory address mode
void IMP(); void ZP0();
void ABS(); void VAL();
void REL(); void DAV();
void DRV(); void RTA();
//cpu instructions
void NOP(); void CLC(); void CLO(); void CLD(); void CLI(); void BRK(); void BRT(); void SEI();
void MOV(); void MR1(); void MR2(); void MR3(); void MR4(); void MSR(); void M1T(); void M2T(); void M3T(); void M4T(); void JJR(); void MJL(); void MJH();
void LOD(); void LDA(); void LD1(); void MUL();
void ADC(); void AC1(); void SBC(); void SC1(); void INT(); void DET(); void IN1(); void DE1(); void INR(); void DER();
void JMP(); void JPR(); void BOE(); void BNE(); void RET();
void BRN(); void BRE(); void BCS(); void BCC(); void BLM(); void BRM(); void BSL(); void BSR();
void CMP(); void CP1(); void CP2(); void RSR();
struct instruction {
uint8_t opcode = 0x00;
void (cpu::* operand)(void) = nullptr;
void (cpu::* loader)(void) = nullptr;
instruction(uint8_t oc, void (cpu::* op)(void), void (cpu::* ad)(void));
instruction() = default;
};
std::array<instruction, 256> lookupTable = { instruction() };
void readInstruction();
instruction current;
public:
cpu();
void onCycle() override;
};

BIN
cpu_design_and_emulator/microprocessor/cpu/customCPU-INSTR.xlsx

266
cpu_design_and_emulator/microprocessor/cpu/instructions.cpp

@ -0,0 +1,266 @@
#include "pch.h"
#include "cpu.h"
void cpu::NOP() {
return;
}
void cpu::CLC() {
setStatus(Carry, 0x0);
}
void cpu::CLO() {
setStatus(Overflow, 0x0);
}
void cpu::CLD() {
setStatus(Decimal, 0x0);
}
void cpu::CLI() {
setStatus(Interrupt, 0x0);
}
void cpu::BRK() {
if (getStatus(Interrupt) == 0x0 || getStatus(Break) == 0x1)
return;
setStatus(Break, 0x1);
m_regRet = m_pc;
m_pc = read(m_addrAbs);
m_pc &= 0x00FF;
m_pc |= 0x0a00;
}
void cpu::BRT() {
m_pc = m_regRet;
setStatus(Break, 0x0);
}
void cpu::MOV() {
write(m_addrAbs, m_regTemp);
}
void cpu::MR1() {
m_regGP[0] = m_regTemp;
}
void cpu::MR2() {
m_regGP[1] = m_regTemp;
}
void cpu::MR3() {
m_regGP[2] = m_regTemp;
}
void cpu::MR4() {
m_regGP[3] = m_regTemp;
}
void cpu::MSR() {
m_regJoined[0] = m_addrAbs;
m_regJoined[1] = m_addrAbs >> 8;
}
void cpu::M1T() {
m_regTemp = m_regGP[0];
}
void cpu::M2T() {
m_regTemp = m_regGP[1];
}
void cpu::M3T() {
m_regTemp = m_regGP[2];
}
void cpu::M4T() {
m_regTemp = m_regGP[3];
}
void cpu::JJR() {
m_pc = m_regJoined[0] | (m_regJoined[1] << 8);
}
void cpu::MJH() {
m_regTemp = m_regJoined[1];
}
void cpu::MJL() {
m_regTemp = m_regJoined[0];
}
void cpu::LOD() {
m_regTemp = read(m_addrAbs);
}
void cpu::LDA() {
write(m_addrAbs, m_regAcc);
}
void cpu::LD1() {
m_regGP[0] = m_regAcc;
}
void cpu::MUL() {
const uint8_t lo = m_addrAbs;
const uint8_t hi = m_addrAbs >> 8;
const uint16_t res = hi * lo;
m_regGP[3] = res;
m_regGP[4] = res >> 8;
}
void cpu::ADC() {
const uint8_t val = read(m_addrAbs);
const uint16_t temp = m_regAcc + val + getStatus(Carry);
const bool carry = temp & 0x0001;
const bool overflow = ~((static_cast<uint16_t>(m_regAcc) ^ static_cast<uint16_t>(val))& (static_cast<uint16_t>(m_regAcc) ^ static_cast<uint16_t>(temp)) & 0x0080);
setStatus(Carry, carry);
setStatus(Overflow, overflow);
setStatus(Negative, temp & 0x80);
if (temp == 0x0000) setStatus(Zero, 0x1);
m_regAcc = temp & 0x00FF;
}
void cpu::AC1() {
const uint8_t val = m_regGP[0];
const uint16_t temp = m_regAcc + val + getStatus(Carry);
const bool carry = temp & 0x0001;
const bool overflow = ~((static_cast<uint16_t>(m_regAcc) ^ static_cast<uint16_t>(val))& (static_cast<uint16_t>(m_regAcc) ^ static_cast<uint16_t>(temp)) & 0x0080);
setStatus(Carry, carry);
setStatus(Overflow, overflow);
setStatus(Negative, temp & 0x80);
if (temp == 0x0000) setStatus(Zero, 0x1);
m_regAcc = temp & 0x00FF;
}
void cpu::SBC() {
const uint8_t val = read(m_addrAbs) ^ 0x00ff;
const uint16_t temp = m_regAcc + val + getStatus(Carry);
const bool carry = temp & 0x0001;
const bool overflow = ~((static_cast<uint16_t>(m_regAcc) ^ static_cast<uint16_t>(val))& (static_cast<uint16_t>(m_regAcc) ^ static_cast<uint16_t>(temp)) & 0x0080);
setStatus(Carry, carry);
setStatus(Overflow, overflow);
setStatus(Negative, temp & 0x80);
if (temp == 0x0000) setStatus(Zero, 0x1);
m_regAcc = temp & 0x00FF;
}
void cpu::SC1() {
const uint8_t val = m_regGP[0] ^ 0x00ff;
const uint16_t temp = m_regAcc + val + getStatus(Carry);
const bool carry = temp & 0x0001;
const bool overflow = ~((static_cast<uint16_t>(m_regAcc) ^ static_cast<uint16_t>(val))& (static_cast<uint16_t>(m_regAcc) ^ static_cast<uint16_t>(temp)) & 0x0080);
setStatus(Carry, carry);
setStatus(Overflow, overflow);
setStatus(Negative, temp & 0x80);
if (temp == 0x0000) setStatus(Zero, 0x1);
m_regAcc = temp & 0x00FF;
}
void cpu::INT() {
m_regTemp = read(m_addrAbs) + 1;
}
void cpu::INR() {
write(m_addrAbs, read(m_addrAbs) + 1);
}
void cpu::IN1() {
m_regGP[0]++;
}
void cpu::DET() {
if (m_regGP[0] == 0x00) setStatus(Negative, 0x1);
m_regTemp = read(m_addrAbs) - 1;
if (m_regGP[0] == 0x00) setStatus(Zero, 0x1);
}
void cpu::DER() {
if (m_regGP[0] == 0x00) setStatus(Negative, 0x1);
write(m_addrAbs, read(m_addrAbs) - 1);
if (m_regGP[0] == 0x00) setStatus(Zero, 0x1);
}
void cpu::DE1() {
if (m_regGP[0] == 0x00) setStatus(Negative, 0x1);
m_regGP[0]--;
if (m_regGP[0] == 0x00) setStatus(Zero, 0x1);
}
void cpu::JMP() {
m_pc = read(m_addrAbs);
}
void cpu::JPR() {
if (getStatus(Interrupt) == 0x1)
return;
m_regRet = m_pc;
m_pc = read(m_addrAbs);
}
void cpu::BOE() {
if (m_regTemp == m_regGP[0]) m_pc = m_addrAbs;
}
void cpu::BNE() {
if (m_regTemp != m_regGP[0]) m_pc = m_addrAbs;
}
void cpu::RET() {
if (m_regRet != 0x0000) m_pc = m_regRet;
}
void cpu::BRE() {
if (m_regGP[0] == m_regGP[1]) m_pc += m_addrRel;
}
void cpu::BRN() {
if (m_regGP[0] != m_regGP[1]) m_pc += m_addrRel;
}
void cpu::BCS() {
if (getStatus(Carry) == 0x1) m_pc += m_addrRel;
}
void cpu::BCC() {
if (getStatus(Carry) == 0x0) m_pc += m_addrRel;
}
void cpu::BLM() {
write(m_addrAbs, read(m_addrAbs) < 1);
}
void cpu::BRM() {
write(m_addrAbs, read(m_addrAbs) > 1);
}
void cpu::BSL() {
m_regTemp = read(m_addrAbs) < 1;
}
void cpu::BSR() {
m_regTemp = read(m_addrAbs) > 1;
}
void cpu::CMP() {
if (m_regAcc == read(m_addrAbs)) setStatus(Z, 0x1);
else if (m_regAcc < read(m_addrAbs)) setStatus(N, 0x1);
else setStatus(C, 0x1);
}
void cpu::CP1() {
if (m_regGP[0] == read(m_addrAbs)) setStatus(Z, 0x1);
else if (m_regGP[0] < read(m_addrAbs)) setStatus(N, 0x1);
else setStatus(C, 0x1);
}
void cpu::CP2() {
if (m_regGP[1] == read(m_addrAbs)) setStatus(Z, 0x1);
else if (m_regGP[1] < read(m_addrAbs)) setStatus(N, 0x1);
else setStatus(C, 0x1);
}
void cpu::RSR() {
uint8_t stat = m_regTemp & 0x0F;
m_regGP[m_regTemp >> 4] = getStatus(statusFlag(stat));
}

3
cpu_design_and_emulator/microprocessor/input/input_handler.cpp

@ -0,0 +1,3 @@
#include "pch.h"
#include "input_handler.h"

3
cpu_design_and_emulator/microprocessor/input/input_handler.h

@ -0,0 +1,3 @@
#pragma once
#include "pch.h"
#include "../microprocessor.h"

14
cpu_design_and_emulator/microprocessor/microprocessor.cpp

@ -0,0 +1,14 @@
#include "pch.h"
#include "microprocessor.h"
uint8_t microprocessor::read(const uint16_t& address) {
return m_parentBus->read(address);
}
void microprocessor::write(const uint16_t& address, const uint8_t& value) {
m_parentBus->write(address, value);
}
void microprocessor::attach(bus* bus_in) {
m_parentBus = bus_in;
}

17
cpu_design_and_emulator/microprocessor/microprocessor.h

@ -0,0 +1,17 @@
#pragma once
#include "pch.h"
#include "../bus/bus.h"
class microprocessor : buselement {
private:
bus* m_parentBus = nullptr;
public:
uint8_t read(const uint16_t& address) override;
void write(const uint16_t& address, const uint8_t& value) override;
microprocessor() = default;
virtual void onCycle() = 0;
void attach(bus* bus_in);
};

2
cpu_design_and_emulator/microprocessor/output/output_processor.cpp

@ -0,0 +1,2 @@
#include "pch.h"
#include "output_processor.h"

2
cpu_design_and_emulator/microprocessor/output/output_processor.h

@ -0,0 +1,2 @@
#pragma once
#include "pch.h"

1
cpu_design_and_emulator/pch.cpp

@ -0,0 +1 @@
#include "pch.h"

5
cpu_design_and_emulator/pch.h

@ -0,0 +1,5 @@
#pragma once
#include <cstdint>
#include <vector>
#include <array>
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