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This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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bachelor-thesis/qdp_project/evaluation-results/current/qdp-xeonmax-dram-tca2-tcb0-...

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change config to allow 64 threads for stage 1 and 32 for stage 2 in all benchmarks
11 months ago
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  1. run;rt-ns;rt-s;result[0];scana-run;scana-wait;scanb-run;scanb-wait;aggrj-run;aggrj-wait;cache-hr;
  2. 0;130276360;0.130276;13289362112;51067414;1471175;0;0;49283144;59563687;0;
  3. 1;131976814;0.131977;13289362112;49345334;1609271;0;0;50813864;58021831;0;
  4. 2;130503411;0.130503;13289362112;47780374;328584;0;0;50235899;57034806;0;
  5. 3;132307450;0.132307;13289362112;45878311;680949;0;0;52347451;57573212;0;
  6. 4;130835433;0.130835;13289362112;48214243;1474290;0;0;56024974;57700141;0;