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This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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change config to allow 64 threads for stage 1 and 32 for stage 2 in all benchmarks
11 months ago
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  1. run;rt-ns;rt-s;result[0];scana-run;scana-wait;scanb-run;scanb-wait;aggrj-run;aggrj-wait;cache-hr;
  2. 0;161461070;0.161461;13289362112;93714454;1678483;20188433;2603;51031809;93944992;0.894531;
  3. 1;162441540;0.162442;13289362112;84040266;1240262;30362251;2435;60783325;84542019;0.751953;
  4. 2;158076422;0.158076;13289362112;96819640;1319758;22143893;2607;45556303;99121803;0.904297;
  5. 3;159321070;0.159321;13289362112;95894287;1597200;15133892;2760;46301687;97342642;0.929688;
  6. 4;157285531;0.157286;13289362112;98728934;889103;17457365;2415;45724511;99122551;0.988281;