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This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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change config to allow 64 threads for stage 1 and 32 for stage 2 in all benchmarks
11 months ago
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  1. run;rt-ns;rt-s;result[0];scana-run;scana-wait;scanb-run;scanb-wait;aggrj-run;aggrj-wait;cache-hr;
  2. 0;104755859;0.104756;13289362112;53955978;1138325;26029418;1932;35566189;56891125;0.835938;
  3. 1;105378092;0.105378;13289362112;56651324;443002;9916642;5539;33454028;58295527;0.992188;
  4. 2;114741880;0.114742;13289362112;54534784;100184;29147109;2259;45425742;57166033;0.953125;
  5. 3;103951538;0.103952;13289362112;56348244;418094;23578848;1723;33404306;57690780;0.917969;
  6. 4;103784415;0.103784;13289362112;57387858;293250;18853900;1855;30177580;59823061;0.960938;