This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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  1. \newglossaryentry{iommu}{
  2. name={IOMMU},
  3. long={Input/Output Memory Management Unit},
  4. first={Input/Output Memory Management Unit (IOMMU)},
  5. description={... desc ...}
  6. }
  7. \newglossaryentry{atc}{
  8. name={ATC},
  9. long={Address Translation Cache},
  10. first={Address Translation Cache (ATC)},
  11. description={... desc ...}
  12. }
  13. \newglossaryentry{bar}{
  14. name={BAR},
  15. long={Base Address Register},
  16. first={Base Address Register (BAR)},
  17. description={... desc ...}
  18. }
  19. \newglossaryentry{dsa}{
  20. name={DSA},
  21. long={Intel Data Streaming Accelerator},
  22. first={Intel Data Streaming Accelerator (DSA)},
  23. description={... desc ...}
  24. }
  25. \newglossaryentry{dsa:wq}{
  26. name={WQ},
  27. long={Work Queue},
  28. first={Work Queue (WQ)},
  29. description={... desc ...}
  30. }
  31. \newglossaryentry{dsa:swq}{
  32. name={SWQ},
  33. long={Shared Work Queue},
  34. first={Shared Work Queue (SWQ)},
  35. description={... desc ...}
  36. }
  37. \newglossaryentry{dsa:dwq}{
  38. name={DWQ},
  39. long={Dedicated Work Queue},
  40. first={Dedicated Work Queue (DWQ)},
  41. description={... desc ...}
  42. }
  43. \newglossaryentry{pcie-dmr}{
  44. name={DMR},
  45. long={PCIe Deferrable Memory Write Request},
  46. first={PCIe Deferrable Memory Write Request (DMR)},
  47. description={... desc ...}
  48. }
  49. \newglossaryentry{x86:enqcmd}{
  50. name={ENQCMD},
  51. long={x86 Instruction ENQCMD},
  52. first={x86 Instruction ENQCMD},
  53. description={... desc ...}
  54. }
  55. \newglossaryentry{x86:movdir64b}{
  56. name={MOVDIR64B},
  57. long={x86 Instruction MOVDIR64B},
  58. first={x86 Instruction MOVDIR64B},
  59. description={... desc ...}
  60. }
  61. \newglossaryentry{x86:pasid}{
  62. name={PASID},
  63. long={Process Address Space ID},
  64. first={Process Address Space ID (PASID)},
  65. description={... desc ...}
  66. }
  67. \newglossaryentry{intel:dml}{
  68. name={Intel DML},
  69. long={Intel Data Mover Library},
  70. first={Intel Data Mover Library (Intel DML)},
  71. description={... desc ...}
  72. }
  73. \newglossaryentry{numa}{
  74. name={NUMA},
  75. long={Non Uniform Memory Architecture},
  76. first={Non Uniform Memory Architecture (NUMA)},
  77. description={... desc ...}
  78. }
  79. \newglossaryentry{numa:node}{
  80. name={Node},
  81. long={NUMA-Node},
  82. first={NUMA-Node (Node)},
  83. description={... desc ...}
  84. }
  85. \newglossaryentry{hbm}{
  86. name={HBM},
  87. long={High Bandwidth Memory},
  88. first={High Bandwidth Memory (HBM)},
  89. description={... desc ...}
  90. }
  91. \newglossaryentry{dram}{
  92. name={DDR-SDRAM},
  93. long={Double Data Rate Synchronous Dynamic Random Access Memory},
  94. first={Double Data Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM)},
  95. description={... desc ...}
  96. }
  97. \newglossaryentry{qdp}{
  98. name={QdP},
  99. long={Query-driven Prefetching},
  100. first={Query-driven Prefetching (QdP)},
  101. description={... desc ...}
  102. }