This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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  1. #include <iostream>
  2. #include <random>
  3. #include <vector>
  4. #include <string>
  5. #include <omp.h>
  6. #include "cache.hpp"
  7. dsacache::Cache CACHE;
  8. void InitCache(const std::string& device) {
  9. if (device == "default") {
  10. auto cache_policy = [](const int numa_dst_node, const int numa_src_node, const size_t data_size) {
  11. return numa_dst_node;
  12. };
  13. auto copy_policy = [](const int numa_dst_node, const int numa_src_node) {
  14. return std::vector<int>{ numa_src_node, numa_dst_node };
  15. };
  16. CACHE.Init(cache_policy,copy_policy);
  17. }
  18. else if (device == "xeonmax") {
  19. auto cache_policy = [](const int numa_dst_node, const int numa_src_node, const size_t data_size) {
  20. return numa_dst_node < 8 ? numa_dst_node + 8 : numa_dst_node;
  21. };
  22. auto copy_policy = [](const int numa_dst_node, const int numa_src_node) {
  23. const bool same_socket = ((numa_dst_node ^ numa_src_node) & 4) == 0;
  24. if (same_socket) {
  25. const bool socket_number = numa_dst_node >> 2;
  26. if (socket_number == 0) return std::vector<int>{ 0, 1, 2, 3 };
  27. else return std::vector<int>{ 4, 5, 6, 7 };
  28. }
  29. else return std::vector<int>{ numa_src_node, numa_dst_node };
  30. };
  31. CACHE.Init(cache_policy,copy_policy);
  32. }
  33. else {
  34. std::cerr << "Given device '" << device << "' not supported!" << std::endl;
  35. exit(-1);
  36. }
  37. }
  38. uint8_t* GetRandomArray(const size_t size) {
  39. uint8_t* array = new uint8_t[size];
  40. std::uniform_int_distribution<uint8_t> unif(std::numeric_limits<uint8_t>::min(), std::numeric_limits<uint8_t>::max());
  41. std::default_random_engine re;
  42. for (size_t i = 0; i < size; i++) {
  43. array[i] = unif(re);
  44. }
  45. return array;
  46. }
  47. bool IsEqual(const uint8_t* a, const uint8_t* b, const size_t size) {
  48. for (size_t i = 0; i < size; i++) {
  49. try {
  50. if (a[i] != b[i]) return false;
  51. }
  52. catch (...) {
  53. return false;
  54. }
  55. }
  56. return true;
  57. }
  58. std::unique_ptr<dsacache::CacheData> PerformAccessAndTest(uint8_t* src, const size_t size, const int tid) {
  59. std::unique_ptr<dsacache::CacheData> data_cache = CACHE.Access(
  60. reinterpret_cast<uint8_t *>(src),
  61. size * sizeof(uint8_t)
  62. );
  63. uint8_t* cached_imm = reinterpret_cast<uint8_t *>(data_cache->GetDataLocation());
  64. // check the value immediately just to see if ram or cache was returned
  65. if (src == cached_imm) {
  66. std::cout << "[" << tid << "] Caching did not immediately yield different data location." << std::endl;
  67. }
  68. else if (cached_imm == nullptr) {
  69. std::cout << "[" << tid << "] Immediately got nullptr." << std::endl;
  70. }
  71. else {
  72. std::cout << "[" << tid << "] Immediately got different data location." << std::endl;
  73. }
  74. // waits for the completion of the asynchronous caching operation
  75. data_cache->WaitOnCompletion();
  76. // gets the cache-data-location from the struct
  77. uint8_t* cached = reinterpret_cast<uint8_t *>(data_cache->GetDataLocation());
  78. // tests on the resulting value
  79. if (src == cached) {
  80. std::cout << "[" << tid << "] Caching did not affect data location." << std::endl;
  81. }
  82. else if (cached == nullptr) {
  83. std::cerr << "[" << tid << "] Got nullptr from cache." << std::endl;
  84. }
  85. else {
  86. std::cout << "[" << tid << "] Got different data location from cache." << std::endl;
  87. }
  88. if (IsEqual(src,cached,size)) {
  89. std::cout << "[" << tid << "] Cached data is correct." << std::endl;
  90. }
  91. else {
  92. std::cerr << "[" << tid << "] Cached data is wrong." << std::endl;
  93. }
  94. return std::move(data_cache);
  95. }
  96. void RunTestST(const size_t size) {
  97. uint8_t* data = GetRandomArray(size);
  98. static constexpr int tid = 0;
  99. std::cout << "[" << tid << "] first access --- " << std::endl;
  100. PerformAccessAndTest(data, size, tid);
  101. std::cout << "[" << tid << "] second access --- " << std::endl;
  102. PerformAccessAndTest(data, size, tid);
  103. std::cout << "[" << tid << "] end of application --- " << std::endl;
  104. }
  105. void RunTestMT(const size_t size) {
  106. uint8_t* data = GetRandomArray(size);
  107. #pragma omp parallel
  108. {
  109. const int tid = omp_get_thread_num();
  110. std::cout << "[" << tid << "] first access --- " << std::endl;
  111. PerformAccessAndTest(data, size, tid);
  112. std::cout << "[" << tid << "] second access --- " << std::endl;
  113. PerformAccessAndTest(data, size, tid);
  114. std::cout << "[" << tid << "] end of block --- " << std::endl;
  115. }
  116. }
  117. void RunTestFlush(const size_t size) {
  118. uint8_t* data1 = GetRandomArray(size);
  119. uint8_t* data2 = GetRandomArray(size);
  120. uint8_t* data3 = GetRandomArray(size);
  121. static constexpr int tid = 0;
  122. std::cout << "[" << tid << "] first access to data d1 and keepalive --- " << std::endl;
  123. const auto c1 = PerformAccessAndTest(data1, size, tid);
  124. std::cout << "[" << tid << "] second access to d2 lets d2 vanish --- " << std::endl;
  125. PerformAccessAndTest(data2, size, tid);
  126. std::cout << "[" << tid << "] third access to d3 should clear d2 --- " << std::endl;
  127. PerformAccessAndTest(data3, size, tid);
  128. std::cout << "[" << tid << "] end of block and test d1 == cache1 --- " << std::endl;
  129. if (IsEqual(data1, c1->GetDataLocation(), size)) {
  130. std::cout << "[" << tid << "] Cached d1 is still correct." << std::endl;
  131. }
  132. else {
  133. std::cerr << "[" << tid << "] Cached d1 is bad." << std::endl;
  134. }
  135. }
  136. int main(int argc, char **argv) {
  137. if (argc != 4) {
  138. std::cerr << "This application requires three parameters!" << std::endl;
  139. std::cout << "Please provide the following positional arguments: [device] [mode] [size]" << std::endl;
  140. std::cout << "[device] from { default, xeonmax } which influences cache and execution placement" << std::endl;
  141. std::cout << "[mode] from { st, mt, flt } or single and multi threaded and flushtest respectively" << std::endl;
  142. std::cout << "[size] positive integral number, amount of bytes in data array" << std::endl;
  143. std::cout << "for flushtest the given size should be 1/3 of the available cache size" << std::endl;
  144. exit(-1);
  145. }
  146. const std::string device = argv[1];
  147. const std::string mode = argv[2];
  148. const std::string size_s = argv[3];
  149. uint32_t size = 0;
  150. try {
  151. size = std::stoul(size_s);
  152. }
  153. catch (...) {
  154. std::cerr << "Given Size '" << size_s << "' caused error during conversion to number!" << std::endl;
  155. }
  156. InitCache(device);
  157. if (mode == "st") {
  158. RunTestST(size);
  159. }
  160. else if (mode == "mt") {
  161. RunTestMT(size);
  162. }
  163. else if (mode == "flt") {
  164. RunTestFlush(size);
  165. }
  166. else {
  167. std::cerr << "Given Mode '" << mode << "' not supported!" << std::endl;
  168. exit(-1);
  169. }
  170. }