This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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  1. \newglossaryentry{iommu}{
  2. short={IOMMU},
  3. name={IOMMU},
  4. long={Input/Output Memory Management Unit},
  5. first={Input/Output Memory Management Unit (IOMMU)},
  6. description={... desc ...}
  7. }
  8. \newglossaryentry{atc}{
  9. short={ATC},
  10. name={ATC},
  11. long={Address Translation Cache},
  12. first={Address Translation Cache (ATC)},
  13. description={... desc ...}
  14. }
  15. \newglossaryentry{bar}{
  16. short={BAR},
  17. name={BAR},
  18. long={Base Address Register},
  19. first={Base Address Register (BAR)},
  20. description={... desc ...}
  21. }
  22. \newglossaryentry{dsa}{
  23. short={DSA},
  24. name={DSA},
  25. long={Intel Data Streaming Accelerator},
  26. first={Intel Data Streaming Accelerator (DSA)},
  27. description={... desc ...}
  28. }
  29. \newglossaryentry{dsa:wq}{
  30. short={WQ},
  31. name={WQ},
  32. long={Work Queue},
  33. first={Work Queue (WQ)},
  34. description={... desc ...}
  35. }
  36. \newglossaryentry{dsa:swq}{
  37. short={SWQ},
  38. name={SWQ},
  39. long={Shared Work Queue},
  40. first={Shared Work Queue (SWQ)},
  41. description={... desc ...}
  42. }
  43. \newglossaryentry{dsa:dwq}{
  44. short={DWQ},
  45. name={DWQ},
  46. long={Dedicated Work Queue},
  47. first={Dedicated Work Queue (DWQ)},
  48. description={... desc ...}
  49. }
  50. \newglossaryentry{pcie-dmr}{
  51. short={DMR},
  52. name={DMR},
  53. long={PCIe Deferrable Memory Write Request},
  54. first={PCIe Deferrable Memory Write Request (DMR)},
  55. description={... desc ...}
  56. }
  57. \newglossaryentry{x86:enqcmd}{
  58. short={ENQCMD},
  59. name={ENQCMD},
  60. long={x86 Instruction ENQCMD},
  61. first={x86 Instruction ENQCMD},
  62. description={... desc ...}
  63. }
  64. \newglossaryentry{x86:movdir64b}{
  65. short={MOVDIR64B},
  66. name={MOVDIR64B},
  67. long={x86 Instruction MOVDIR64B},
  68. first={x86 Instruction MOVDIR64B},
  69. description={... desc ...}
  70. }
  71. \newglossaryentry{x86:pasid}{
  72. short={PASID},
  73. name={PASID},
  74. long={Process Address Space ID},
  75. first={Process Address Space ID (PASID)},
  76. description={... desc ...}
  77. }
  78. \newglossaryentry{intel:dml}{
  79. short={Intel DML},
  80. name={Intel DML},
  81. long={Intel Data Mover Library},
  82. first={Intel Data Mover Library (Intel DML)},
  83. description={... desc ...}
  84. }
  85. \newglossaryentry{numa}{
  86. short={NUMA},
  87. name={NUMA},
  88. long={Non Uniform Memory Architecture},
  89. first={Non Uniform Memory Architecture (NUMA)},
  90. description={... desc ...}
  91. }
  92. \newglossaryentry{numa:node}{
  93. short={Node},
  94. name={Node},
  95. long={NUMA-Node},
  96. first={NUMA-Node (Node)},
  97. description={... desc ...}
  98. }
  99. \newglossaryentry{hbm}{
  100. short={HBM},
  101. name={HBM},
  102. long={High Bandwidth Memory},
  103. first={High Bandwidth Memory (HBM)},
  104. description={... desc ...}
  105. }
  106. \newglossaryentry{dram}{
  107. short={DDR-SDRAM},
  108. name={DDR-SDRAM},
  109. long={Double Data Rate Synchronous Dynamic Random Access Memory},
  110. first={Double Data Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM)},
  111. description={... desc ...}
  112. }
  113. \newglossaryentry{qdp}{
  114. short={QdP},
  115. name={QdP},
  116. long={Query-driven Prefetching},
  117. first={Query-driven Prefetching (QdP)},
  118. description={... desc ...}
  119. }