This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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  1. \newglossaryentry{iommu}{
  2. name={IOMMU},
  3. description={... desc ...},
  4. first={Input/Output Memory Management Unit (IOMMU)},
  5. long={Input/Output Memory Management Unit}
  6. }
  7. \newglossaryentry{bar}{
  8. name={BAR},
  9. description={... desc ...},
  10. first={Base Address Register (BAR)},
  11. long={Base Address Register}
  12. }
  13. \newglossaryentry{dsa}{
  14. name={DSA},
  15. description={... desc ...},
  16. first={Intel Data Streaming Accelerator (DSA)},
  17. long={Intel Data Streaming Accelerator}
  18. }