This contains my bachelors thesis and associated tex files, code snippets and maybe more.
Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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\begin{tabular}{lll}\topruleConfiguration & Speedup & Cache Hitrate \\\midruleDDR-SDRAM (Baseline) & x1.00 & \textemdash \\HBM (Upper Limit) & x1.41 & \textemdash \\Prefetching & x0.82 & 89.38 \% \\Prefetching, Distributed Columns & x1.23 & 93.20 \% \\\bottomrule\end{tabular}
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