description={\textsc{\glsentrylong{bar}:} \todo{write bar description}}
}
}
\newglossaryentry{dsa}{
\newglossaryentry{dsa}{
@ -27,7 +27,7 @@
name={DSA},
name={DSA},
long={Intel Data Streaming Accelerator},
long={Intel Data Streaming Accelerator},
first={Intel Data Streaming Accelerator (DSA)},
first={Intel Data Streaming Accelerator (DSA)},
description={... desc ...}
description={\textsc{\glsentrylong{dsa}:} A component of modern Intel server processors, capable of executing common data operations asynchronously and thereby offloading them from the CPU.}
}
}
\newglossaryentry{dsa:wq}{
\newglossaryentry{dsa:wq}{
@ -35,7 +35,7 @@
name={WQ},
name={WQ},
long={Work Queue},
long={Work Queue},
first={Work Queue (WQ)},
first={Work Queue (WQ)},
description={... desc ...}
description={\textsc{\glsentrylong{dsa:wq}:} Architectural component of the \gls{dsa} to which data is submitted by the user. See Section \ref{subsec:state:dsa-arch-comp} for more detail on its function.}
}
}
\newglossaryentry{dsa:swq}{
\newglossaryentry{dsa:swq}{
@ -43,7 +43,7 @@
name={SWQ},
name={SWQ},
long={Shared Work Queue},
long={Shared Work Queue},
first={Shared Work Queue (SWQ)},
first={Shared Work Queue (SWQ)},
description={... desc ...}
description={\textsc{\glsentrylong{dsa:swq}:} A type of Work Queue to which submissions are implicitly synchronized, allowing safe usage from multiple processes. See Section \ref{subsec:state:dsa-arch-comp} for more detail.}
}
}
\newglossaryentry{dsa:dwq}{
\newglossaryentry{dsa:dwq}{
@ -51,7 +51,7 @@
name={DWQ},
name={DWQ},
long={Dedicated Work Queue},
long={Dedicated Work Queue},
first={Dedicated Work Queue (DWQ)},
first={Dedicated Work Queue (DWQ)},
description={... desc ...}
description={\textsc{\glsentrylong{dsa:dwq}:} A type of Work Queue only usable by one process, and therefore with potentially lower submission overhead. See Section \ref{subsec:state:dsa-arch-comp} for more detail.}
description={\textsc{\glsentrylong{x86:pasid}:} Identifier used by the \glsentryshort{dsa} in conjunction with the \glsentryshort{iommu} to resolve virtual addresses. See Section \ref{subsubsec:state:dsa-vaddr}.}
}
}
\newglossaryentry{intel:dml}{
\newglossaryentry{intel:dml}{
@ -91,7 +91,7 @@
name={Intel DML},
name={Intel DML},
long={Intel Data Mover Library},
long={Intel Data Mover Library},
first={Intel Data Mover Library (Intel DML)},
first={Intel Data Mover Library (Intel DML)},
description={... desc ...}
description={\textsc{\glsentrylong{intel:dml}:} A library presenting a high-level interface with the \glsentryshort{dsa}. View the usage example in Section \ref{sec:state:dml} or the library documentation \cite{intel:dmldoc} for further information.}
}
}
\newglossaryentry{numa}{
\newglossaryentry{numa}{
@ -99,7 +99,7 @@
name={NUMA},
name={NUMA},
long={Non-Uniform Memory Architecture},
long={Non-Uniform Memory Architecture},
first={Non-Uniform Memory Architecture (NUMA)},
first={Non-Uniform Memory Architecture (NUMA)},
description={... desc ...}
description={\textsc{\glsentrylong{numa}:} Describes a system architecture organized into different Nodes with each node observing different access patterns to memory for the available address range.}
}
}
\newglossaryentry{numa:node}{
\newglossaryentry{numa:node}{
@ -107,7 +107,7 @@
name={Node},
name={Node},
long={NUMA-Node},
long={NUMA-Node},
first={NUMA-Node (Node)},
first={NUMA-Node (Node)},
description={... desc ...}
description={\textsc{\glsentrylong{numa:node}:} A Node in a NUMA-system. See the Entry for NUMA for an explanation of both.}
}
}
\newglossaryentry{hbm}{
\newglossaryentry{hbm}{
@ -115,7 +115,7 @@
name={HBM},
name={HBM},
long={High Bandwidth Memory},
long={High Bandwidth Memory},
first={High Bandwidth Memory (HBM)},
first={High Bandwidth Memory (HBM)},
description={... desc ...}
description={\textsc{\glsentrylong{hbm}:} Main memory technology, consisting of stacked DRAM-dies. Section \ref{sec:state:hbm} offers more detail.}
}
}
\newglossaryentry{dram}{
\newglossaryentry{dram}{
@ -123,7 +123,7 @@
name={DDR-SDRAM},
name={DDR-SDRAM},
long={Double Data Rate Synchronous Dynamic Random Access Memory},
long={Double Data Rate Synchronous Dynamic Random Access Memory},
first={Double Data Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM)},
first={Double Data Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM)},
description={... desc ...}
description={\textsc{\glsentrylong{dram}:} Main memory technology found in common computer systems.}
}
}
\newglossaryentry{qdp}{
\newglossaryentry{qdp}{
@ -131,13 +131,14 @@
name={QdP},
name={QdP},
long={Query-driven Prefetching},
long={Query-driven Prefetching},
first={Query-driven Prefetching (QdP)},
first={Query-driven Prefetching (QdP)},
description={... desc ...}
description={\textsc{\glsentrylong{qdp}:} Methodology to determine database columns worth prefetching to cache in order to accelerate a queries. Described in Section \ref{sec:state:qdp}.}
}
}
\newglossaryentry{mempress}{
\newglossaryentry{mempress}{
short={memory pressure},
short={memory pressure},
name={Memory Pressure},
name={Memory Pressure},
description={... desc ...}
long={Memory Pressure},
description={\textsc{\glsentrylong{mempress}:} Situation where high memory utilization is encountered.}
}
}
\newglossaryentry{api}{
\newglossaryentry{api}{
@ -145,13 +146,14 @@
name={API},
name={API},
long={Application Programming Interface},
long={Application Programming Interface},
first={Application Programming Interface (API)},
first={Application Programming Interface (API)},
description={... desc ...}
description={\textsc{\glsentrylong{api}:} Public functions exposed by a library, through which programs utilizing this library can interact with it.}