diff --git a/thesis/bachelor.pdf b/thesis/bachelor.pdf
index 55232ee..fa84e0c 100644
Binary files a/thesis/bachelor.pdf and b/thesis/bachelor.pdf differ
diff --git a/thesis/content/20_state.tex b/thesis/content/20_state.tex
index 16960bf..7740917 100644
--- a/thesis/content/20_state.tex
+++ b/thesis/content/20_state.tex
@@ -115,7 +115,6 @@ While a process could theoretically submit work to the \gls{dsa} by manually pre
 \section{Programming Interface for \glsentrylong{dsa}}
 \label{sec:state:dml}
 
-\ref{sec:}
 As mentioned in Section \ref{subsec:state:dsa-software-view}, \gls{intel:dml} offers a high level interface for interacting with the hardware accelerator, specifically Intel \gls{dsa}. Opting for the C++ interface, we will now demonstrate its usage by example of a simple memcopy implementation for the \gls{dsa}. \par
 
 \begin{figure}[!t]
diff --git a/thesis/content/60_evaluation.tex b/thesis/content/60_evaluation.tex
index 0dd3d49..b1d9084 100644
--- a/thesis/content/60_evaluation.tex
+++ b/thesis/content/60_evaluation.tex
@@ -107,7 +107,7 @@ In Section \ref{sec:eval:expectations}, we anticipated that the simple query wou
 
 The necessity to distribute data across \gls{numa:node}s is seen as practical, given that developers commonly apply this optimization to leverage the available memory bandwidth of \glsentrylong{numa}s. Consequently, the \texttt{Cache} has demonstrated its effectiveness by achieving a respectable speed-up positioned directly between the baseline and the theoretical upper limit (see Table \ref{table:qdp-speedup}). \par
 
-As stated in Section \ref{sec:design:cache}, the decision to design and implement a cache instead of focusing solely on prefetching was made to enhance the usefulness of this work's contribution. While our tests were conducted on a system with \gls{hbm}, other advancements in main memory technologies, such as \gls{nvram}, were not considered. Despite the public functions of the \texttt{Cache} being named with cache usage in mind, its utility extends beyond this scope, providing flexibility through the policy functions, described in Section \ref{sec:design:accel-usage}. Potential applications include replication to \gls{nvram} for data loss prevention. Therefore, we consider the increase in design complexity to be a worthwhile trade-off, providing a significant contribution to the field of heterogeneous memory systems. \par
+As stated in Chapter \ref{chap:design}, the decision to design and implement a cache instead of focusing solely on prefetching was made to enhance the usefulness of this work's contribution. While our tests were conducted on a system with \gls{hbm}, other advancements in main memory technologies, such as \gls{nvram}, were not considered. Despite the public functions of the \texttt{Cache} being named with cache usage in mind, its utility extends beyond this scope, providing flexibility through the policy functions, described in Section \ref{subsec:design:policy-functions}. Potential applications include replication to \gls{nvram} for data loss prevention. Therefore, we consider the increase in design complexity to be a worthwhile trade-off, providing a significant contribution to the field of heterogeneous memory systems. \par
 
 
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