@ -80,7 +80,7 @@ Given the file permissions, it would now be possible for a process to submit wor
\item cache control flag in descriptor controls whether writes are directed to cache or to memory \cite[31]{intel:dsaspec} effects on copy from DRAM > HBM unknown
\end{itemize}
\section{HW/SW Setup}
\section{Setup and Configuration}
Give the reader the tools to replicate the setup.
Also explain why the BIOS-configs are required.
@ -94,13 +94,21 @@ Setup Requirements:
\item kernel option "intel\_iommu=on,sm\_on"
\end{itemize}
\section{Microbenchmarks}
\section{Programming Interface}
\todo{provide microbenchmarks with multiple configurations and for many use cases}
\begin{itemize}
\item choice is intel data mover library
\item two concepts, state-based for c-api and operation-based c++
\item just explain the basics (no code) and refer to dml documentation
\end{itemize}
\section{Evaluation}
\section{Microbenchmarks}
\todo{evaluate the benchmarks and conclude with projected use cases - may use the cases from dsaspec/guide}
\begin{itemize}
\item submit cost analysis: best method and for a subset the point at which submit cost < time savings
\item effect of mt-submit, low because \gls{dsa:swq} implicitly synchronized, bandwidth is shared
\item copy strategy and performance analysis from ddr to HBM
