change config to allow 64 threads for stage 1 and 32 for stage 2 in all benchmarks

11 months ago · a4dac61730
7 changed files with 41 additions and 6 deletions
--- a/qdp_project/evaluation-results/current/qdp-xeonmax-distprefetch-tca1-tcb1-tcj1-tmul32-wl4294967296-cs8388608.csv
+++ b/qdp_project/evaluation-results/current/qdp-xeonmax-distprefetch-tca1-tcb1-tcj1-tmul32-wl4294967296-cs8388608.csv
@ -0,0 +1,6 @@
 run;rt-ns;rt-s;result[0];scana-run;scana-wait;scanb-run;scanb-wait;aggrj-run;aggrj-wait;cache-hr;
 0;104755859;0.104756;13289362112;53955978;1138325;26029418;1932;35566189;56891125;0.835938;
 1;105378092;0.105378;13289362112;56651324;443002;9916642;5539;33454028;58295527;0.992188;
 2;114741880;0.114742;13289362112;54534784;100184;29147109;2259;45425742;57166033;0.953125;
 3;103951538;0.103952;13289362112;56348244;418094;23578848;1723;33404306;57690780;0.917969;
 4;103784415;0.103784;13289362112;57387858;293250;18853900;1855;30177580;59823061;0.960938;
--- a/qdp_project/evaluation-results/current/qdp-xeonmax-dram-tca2-tcb0-tcj1-tmul32-wl4294967296-cs2097152.csv
+++ b/qdp_project/evaluation-results/current/qdp-xeonmax-dram-tca2-tcb0-tcj1-tmul32-wl4294967296-cs2097152.csv
@ -0,0 +1,6 @@
 run;rt-ns;rt-s;result[0];scana-run;scana-wait;scanb-run;scanb-wait;aggrj-run;aggrj-wait;cache-hr;
 0;130276360;0.130276;13289362112;51067414;1471175;0;0;49283144;59563687;0;
 1;131976814;0.131977;13289362112;49345334;1609271;0;0;50813864;58021831;0;
 2;130503411;0.130503;13289362112;47780374;328584;0;0;50235899;57034806;0;
 3;132307450;0.132307;13289362112;45878311;680949;0;0;52347451;57573212;0;
 4;130835433;0.130835;13289362112;48214243;1474290;0;0;56024974;57700141;0;
--- a/qdp_project/evaluation-results/current/qdp-xeonmax-hbm-tca4-tcb0-tcj1-tmul32-wl4294967296-cs2097152.csv
+++ b/qdp_project/evaluation-results/current/qdp-xeonmax-hbm-tca4-tcb0-tcj1-tmul32-wl4294967296-cs2097152.csv
@ -0,0 +1,6 @@
 run;rt-ns;rt-s;result[0];scana-run;scana-wait;scanb-run;scanb-wait;aggrj-run;aggrj-wait;cache-hr;
 0;93001705;0.0930017;13289362112;33231339;355258;0;0;22569543;47891753;0;
 1;92221590;0.0922216;13289362112;30695511;228538;0;0;21527724;44081716;0;
 2;92560253;0.0925603;13289362112;35451124;536396;0;0;22409100;46648414;0;
 3;92956664;0.0929567;13289362112;32442350;460294;0;0;24038893;44171059;0;
 4;94724810;0.0947248;13289362112;36048241;688918;0;0;21411032;48893316;0;
--- a/qdp_project/evaluation-results/current/qdp-xeonmax-prefetch-tca1-tcb1-tcj1-tmul32-wl4294967296-cs8388608.csv
+++ b/qdp_project/evaluation-results/current/qdp-xeonmax-prefetch-tca1-tcb1-tcj1-tmul32-wl4294967296-cs8388608.csv
@ -0,0 +1,6 @@
 run;rt-ns;rt-s;result[0];scana-run;scana-wait;scanb-run;scanb-wait;aggrj-run;aggrj-wait;cache-hr;
 0;161461070;0.161461;13289362112;93714454;1678483;20188433;2603;51031809;93944992;0.894531;
 1;162441540;0.162442;13289362112;84040266;1240262;30362251;2435;60783325;84542019;0.751953;
 2;158076422;0.158076;13289362112;96819640;1319758;22143893;2607;45556303;99121803;0.904297;
 3;159321070;0.159321;13289362112;95894287;1597200;15133892;2760;46301687;97342642;0.929688;
 4;157285531;0.157286;13289362112;98728934;889103;17457365;2415;45724511;99122551;0.988281;
--- a/qdp_project/evaluation-results/baseline/current-dram/qdp-xeonmax-dram-tca2-tcb0-tcj1-tmul16-wl4294967296-cs2097152.csv
+++ b/qdp_project/evaluation-results/baseline/current-dram/qdp-xeonmax-dram-tca2-tcb0-tcj1-tmul16-wl4294967296-cs2097152.csv
--- a/qdp_project/evaluation-results/baseline/current-hbm/qdp-xeonmax-hbm-tca2-tcb0-tcj1-tmul16-wl4294967296-cs2097152.csv
+++ b/qdp_project/evaluation-results/baseline/current-hbm/qdp-xeonmax-hbm-tca2-tcb0-tcj1-tmul16-wl4294967296-cs2097152.csv
--- a/qdp_project/src/Configuration.hpp
+++ b/qdp_project/src/Configuration.hpp
@ -3,7 +3,7 @@
 #include "utils/memory_literals.h"
 #ifndef MODE_SET_BY_CMAKE
 #define MODE_PREFETCH
 #define MODE_DISTPREFETCH
 #endif
 constexpr size_t WL_SIZE_B = 4_GiB;
@ -13,9 +13,9 @@ constexpr int MEM_NODE_HBM = 8;
 constexpr int MEM_NODE_DRAM = 0;
 #ifdef MODE_PREFETCH
 constexpr uint32_t GROUP_COUNT = 16;
 constexpr uint32_t GROUP_COUNT = 32;
 constexpr size_t CHUNK_SIZE_B = 8_MiB;
 constexpr uint32_t TC_SCANA = 2;
 constexpr uint32_t TC_SCANA = 1;
 constexpr uint32_t TC_SCANB = 1;
 constexpr uint32_t TC_AGGRJ = 1;
 constexpr bool PERFORM_CACHING = true;
@ -23,9 +23,20 @@ constexpr int MEM_NODE_A = 0;
 constexpr int MEM_NODE_B = 0;
 constexpr char MODE_STRING[] = "prefetch";
 #endif
 #ifdef MODE_DISTPREFETCH
 constexpr uint32_t GROUP_COUNT = 32;
 constexpr size_t CHUNK_SIZE_B = 8_MiB;
 constexpr uint32_t TC_SCANA = 1;
 constexpr uint32_t TC_SCANB = 1;
 constexpr uint32_t TC_AGGRJ = 1;
 constexpr bool PERFORM_CACHING = true;
 constexpr int MEM_NODE_A = 0;
 constexpr int MEM_NODE_B = 1;
 constexpr char MODE_STRING[] = "distprefetch";
 #endif
 #ifdef MODE_DRAM
 constexpr size_t CHUNK_SIZE_B = 2_MiB;
 constexpr uint32_t GROUP_COUNT = 16;
 constexpr uint32_t GROUP_COUNT = 32;
 constexpr uint32_t TC_SCANA = 2;
 constexpr uint32_t TC_SCANB = 0;
 constexpr uint32_t TC_AGGRJ = 1;
@ -36,8 +47,8 @@ constexpr char MODE_STRING[] = "dram";
 #endif
 #ifdef MODE_HBM
 constexpr size_t CHUNK_SIZE_B = 2_MiB;
 constexpr uint32_t GROUP_COUNT = 16;
 constexpr uint32_t TC_SCANA = 2;
 constexpr uint32_t GROUP_COUNT = 32;
 constexpr uint32_t TC_SCANA = 4;
 constexpr uint32_t TC_SCANB = 0;
 constexpr uint32_t TC_AGGRJ = 1;
 constexpr bool PERFORM_CACHING = false;