remove bar and atc from glossary and reword where they were used in state, this results in easier to understand sentences and removes unnecessary detail

thesis/content/20_state.tex

@@ -72,7 +72,7 @@ Introduced with the \(4^{th}\) generation of Intel Xeon Scalable Processors, the
     \label{fig:dsa-internal-block}
 \end{figure}
 
-The \gls{dsa} chip is directly integrated into the processor and attaches via the I/O fabric interface, serving as the conduit for all communication. Through this interface, the \gls{dsa} is accessible as a PCIe device. Consequently, configuration utilizes memory-mapped registers set in the devices \gls{bar}. In a system with multiple processing nodes, there may also be one \gls{dsa} per node, resulting in up to four DSA devices per socket in \(4^{th}\) generation Intel Xeon Processors \cite[Sec. 3.1.1]{intel:dsaguide}. To accommodate various use cases, the layout of the \gls{dsa} is software-defined. The structure comprises three components, which we will describe in detail. We also briefly explain how the \gls{dsa} resolves virtual addresses and signals operation completion. At last, we will detail operation execution ordering. \par
+The \gls{dsa} chip is directly integrated into the processor and attaches via the I/O fabric interface, serving as the conduit for all communication. Through this interface, the \gls{dsa} is accessible and configurable as a PCIe device. In a system with multiple processing nodes, there may also be one \gls{dsa} per node, resulting in up to four DSA devices per socket in \(4^{th}\) generation Intel Xeon Processors \cite[Sec. 3.1.1]{intel:dsaguide}. To accommodate various use cases, the layout of the \gls{dsa} is software-defined. The structure comprises three components, which we will describe in detail. We also briefly explain how the \gls{dsa} resolves virtual addresses and signals operation completion. At last, we will detail operation execution ordering. \par
 
 \subsubsection{Architectural Components}
 \label{subsec:state:dsa-arch-comp}

thesis/own.gls

@@ -6,22 +6,6 @@
     description={\textsc{\glsentrylong{iommu}:} \todo{write iomu description}}
 }
 
-\newglossaryentry{atc}{
-    short={ATC},
-    name={ATC},
-    long={Address Translation Cache},
-    first={Address Translation Cache (ATC)},
-    description={\textsc{\glsentrylong{atc}:} \todo{write arc description}}
-}
-
-\newglossaryentry{bar}{
-    short={BAR},
-    name={BAR},
-    long={Base Address Register},
-    first={Base Address Register (BAR)},
-    description={\textsc{\glsentrylong{bar}:} \todo{write bar description}}
-}
-
 \newglossaryentry{dsa}{
     short={DSA},
     name={DSA},
@@ -35,7 +19,7 @@
     name={WQ},
     long={Work Queue},
     first={Work Queue (WQ)},
-    description={\textsc{\glsentrylong{dsa:wq}:}  Architectural component of the \gls{dsa} to which data is submitted by the user. See Section \ref{subsec:state:dsa-arch-comp} for more detail on its function.}
+    description={\textsc{\glsentrylong{dsa:wq}:} Architectural component of the \gls{dsa} to which data is submitted by the user. See Section \ref{subsec:state:dsa-arch-comp} for more detail on its function.}
 }
 
 \newglossaryentry{dsa:swq}{
@@ -125,13 +109,6 @@
     description={\textsc{\glsentrylong{api}:} Definition of the interface provided by an application, enabling interaction between software components or systems.}
 }
 
-\newglossaryentry{remotemem}{
-    short={Remote Memory},
-    name={Remote Memory},
-    long={Remote Memory},
-    description={\textsc{\glsentrylong{remotemem}:} ... desc ... \todo{write remotemem description}}
-}
-
 \newglossaryentry{nvram}{
     short={NVRAM},
     name={NVRAM},