diff --git a/thesis/content/20_state.tex b/thesis/content/20_state.tex
index 913f358..965e86b 100644
--- a/thesis/content/20_state.tex
+++ b/thesis/content/20_state.tex
@@ -1,5 +1,5 @@
 \chapter{Technical Background}
-\label{sec:state}
+\label{chap:state}
 
 % Hier werden zwei wesentliche Aufgaben erledigt:
 
@@ -29,14 +29,23 @@
 % Kapitel wird in der Regel zuerst geschrieben und ist das Einfachste
 % (oder das Schwerste weil erste).
 
+\todo{write introductory paragraph}
+
+\section{High Bandwidth Memory}
+
+\todo{write this section}
+
+\section{Query Driven Prefetching}
+
+\todo{write this section}
+
+\section{Intel Data Streaming Accelerator}
+
 \blockquote{Intel \gls{dsa} is a high-performance data copy and transformation accelerator that will be integrated in future Intel® processors, targeted for optimizing streaming data movement and transformation operations common with applications for high-performance storage, networking, persistent memory, and various data processing applications. \cite[15]{intel:dsaspec}}
 
 Introduced with the 4th generation of Intel Xeon Scalable Processors \cite{intel:xeonbrief}, the \gls{dsa} promises to alleviate the CPU from \enquote{common storage functions and operations such as data integrity checks and deduplication} \cite{intel:xeonbrief}. This chapter will give an overview of the architecture, software and the interaction of these two components. The reader will be familiarized with the setup and equipped with the knowledge to configure the system for a specific use case.
 
 \todo{consider adding projected use cases as in the architecture specification here}
-
-\section{Architecture}
-
 To be able to optimally utilize the Hardware, knowledge of its workings is required to make educated decisions. Therefore, this section describes both the workings of the \gls{dsa} engine itself and the view that is presented through software interfaces. All statements are based on Chapter 3 of the Architecture Specification by Intel \cite{intel:dsaspec}. \par
 
 \subsection{Hardware Architecture} \label{subsection:dsa-hwarch}
@@ -75,12 +84,26 @@ Due to efforts by intel programmers, since Linux Kernel 5.10 \cite[Installation
 
 Given the file permissions, it would now be possible for a process to submit work to the \gls{dsa} via either \gls{x86:movdir64b} or \gls{x86:enqcmd} instructions, providing the descriptors by manually configuring them. This, however, is quite cumbersome, which is why Intels Data Mover Library \cite{intel:dmldoc} exists. With some limitations (like lacking support for \gls{dsa:dwq}s) this library presents a high-level interface that takes care of creation and submission of descriptors, some error handling and reporting. Thanks to the high-level-view the code may choose a different execution path at runtime which allows the memory operations to either be executed in hardware (on a \gls{dsa}) or in software (using equivalent instructions provided by the library) which makes code based upon it automatically compatible with systems that do not provide hardware or software support. \par
 
+\todo{finish this section}
+
 \begin{itemize}
     \item drain descriptor / drain command signals completion of preceding descriptors for fencing in non-batch submissions, in batches the ``fence flag'` can be used to ensure ordering, failures before a fence will lead to the following descriptors being aborted \cite[30]{intel:dsaspec}, \texttt{sfence} or \texttt{mfence} should be executed before pushing drain descriptor \cite[32]{intel:dsaspec}
     \item cache control flag in descriptor controls whether writes are directed to cache or to memory \cite[31]{intel:dsaspec} effects on copy from DRAM > HBM unknown
 \end{itemize}
 
-\section{Setup and Configuration}
+\subsection{Programming Interface}
+
+\todo{write this section}
+
+\begin{itemize}
+    \item choice is intel data mover library
+    \item two concepts, state-based for c-api and operation-based c++
+    \item just explain the basics (no code) and refer to dml documentation
+\end{itemize}
+
+\section{System Setup and Configuration} \label{sec:state:setup-and-config}
+
+\todo{write this section}
 
 Give the reader the tools to replicate the setup.
 Also explain why the BIOS-configs are required.
@@ -92,14 +115,7 @@ Setup Requirements:
     \item IOMMU enabled
     \item kernel with iommu and idxd driver support
     \item kernel option "intel\_iommu=on,sm\_on"
-\end{itemize}
-
-\section{Programming Interface}
-
-\begin{itemize}
-    \item choice is intel data mover library
-    \item two concepts, state-based for c-api and operation-based c++
-    \item just explain the basics (no code) and refer to dml documentation
+    \item numa nodes for hbm access in bios
 \end{itemize}
 
 \cleardoublepage