From cd78e4730dc84d64571fd16ef991e75d9ed05d8a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Constantin=20F=C3=BCrst?= <c@fuersten.info>
Date: Thu, 18 Jan 2024 22:25:11 +0100
Subject: [PATCH] add a paragraph about hbm in the state chapter

---
 thesis/content/20_state.tex |  2 +-
 thesis/own.bib              | 20 +++++++++++++++++++-
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/thesis/content/20_state.tex b/thesis/content/20_state.tex
index 9295278..557221b 100644
--- a/thesis/content/20_state.tex
+++ b/thesis/content/20_state.tex
@@ -33,7 +33,7 @@
 
 \section{High Bandwidth Memory}
 
-\todo{write this section}
+\glsentrylong{hbm} is a novel memory technology promising an increase in peak bandwidth. It is composed of stacked DRAM dies \cite[p. 1]{hbm-arch-paper} and is slowly being integrated into server processors, notably the Intel® Xeon® Max Series \cite{intel:xeonmaxbrief}. \gls{hbm} on these systems may be configured in different memory modes, most notably, HBM Flat Mode and HBM Cache Mode \cite{intel:xeonmaxbrief}. The former gives applications direct control, requiring code changes while the latter utilizes the \gls{hbm} as cache for the systems DDR based main memory \cite{intel:xeonmaxbrief}. \par
 
 \section{Query Driven Prefetching}
 
diff --git a/thesis/own.bib b/thesis/own.bib
index d60b841..ff826c3 100644
--- a/thesis/own.bib
+++ b/thesis/own.bib
@@ -14,6 +14,14 @@
     urldate = {2023-11-15}
 }
 
+@ONLINE{intel:xeonmaxbrief,
+    author = {Intel},
+    title = {{Intel® Xeon® CPU Max Series Product Brief}},
+    date = {2023-01-06},
+    url = {https://www.intel.com/content/www/us/en/content-details/765259/intel-xeon-cpu-max-series-product-brief.html},
+    urldate = {2024-01-18}
+}
+
 @ONLINE{intel:dsaguide,
     author = {Intel},
     title = {{Intel® Data Streaming Accelerator User Guide}},
@@ -127,7 +135,6 @@
     urldate = {2024-01-18}
 }
 
-
 @ONLINE{atomic-wait-details,
     author = {Thomas Rodgers},
     title = {{Implementing C++20 atomic waiting in libstdc++}},
@@ -151,4 +158,15 @@
     date = {2016-12},
     urldate = {2024-01-18},
     url = {https://support.amd.com/TechDocs/24593.pdf}
+}
+
+@INPROCEEDINGS{hbm-arch-paper,
+  author={Jun, Hongshin and Cho, Jinhee and Lee, Kangseol and Son, Ho-Young and Kim, Kwiwook and Jin, Hanho and Kim, Keith},
+  booktitle={2017 IEEE International Memory Workshop (IMW)}, 
+  title={HBM (High Bandwidth Memory) DRAM Technology and Architecture}, 
+  year={2017},
+  volume={},
+  number={},
+  pages={1-4},
+  doi={10.1109/IMW.2017.7939084}
 }
\ No newline at end of file