diff --git a/thesis/bachelor.pdf b/thesis/bachelor.pdf
index 5687131..f2dd32a 100644
Binary files a/thesis/bachelor.pdf and b/thesis/bachelor.pdf differ
diff --git a/thesis/own.bib b/thesis/own.bib
index 246c734..41e4569 100644
--- a/thesis/own.bib
+++ b/thesis/own.bib
@@ -2,7 +2,7 @@
 % Encoding: UTF-8
 
 @ONLINE{intel:dsaspec,
-    author = {Intel},
+    author = {Intel Corporation},
     title = {{Intel® Data Streaming Accelerator Architecture Specification}},
     date = {2022-09-16},
     url = {https://www.intel.com/content/www/us/en/content-details/671116/intel-data-streaming-accelerator-architecture-specification.html},
@@ -10,7 +10,7 @@
 }
 
 @ONLINE{intel:xeonbrief,
-    author = {Intel},
+    author = {Intel Corporation},
     title = {New Intel® Xeon® Platform Includes Built-In Accelerators for Encryption, Compression, and Data Movement},
     date = {2022-12},
     url = {https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2022-12/storage-engines-4th-gen-xeon-brief.pdf},
@@ -18,13 +18,42 @@
 }
 
 @ONLINE{intel:dsaguide,
-    author = {Intel},
+    author = {Intel Corporation},
     title = {{Intel® Data Streaming Accelerator User Guide}},
     date = {2023-01-11},
     url = {https://www.intel.com/content/www/us/en/content-details/759709/intel-data-streaming-accelerator-user-guide.html},
     urldate = {2023-11-15}
 }
 
+@ONLINE{intel:analysis,
+    author = {Reese Kuper et al.},
+    title = {{A Quantitative Analysis and Guideline of Data Streaming Accelerator in Intel® 4th Gen Xeon® Scalable Processors}},
+    date = {2023-05},
+    url = {https://arxiv.org/pdf/2305.02480.pdf},
+    urldate = {2024-01-07}
+}
+
+@ONLINE{intel:idxd-driver-repo,
+    author = {Intel Corporation},
+    title = {{Intel IDXD Driver for Linux Kernel Repository}},
+    url = {https://github.com/intel/idxd-driver},
+    urldate = {2024-01-07}
+}
+
+@ONLINE{intel:libaccel-config-repo,
+    author = {Intel Corporation},
+    title = {{Intel Libaccel-Config Repository}},
+    url = {https://github.com/intel/idxd-config},
+    urldate = {2024-01-07}
+}
+
+@ONLINE{intel:dmldoc,
+    author = {Intel Corporation},
+    title = {{Intel Data Mover Library Documentation}},
+    url = {https://intel.github.io/DML/index.html},
+    urldate = {2024-01-07}
+}
+
 @INPROCEEDINGS{becher04:_feurig_hacken_mit_firew,
    author = {Michael Becher and Maximillian Dornseif},
    title = {{Feuriges Hacken - Spaß mit Firewire}},
diff --git a/thesis/own.gls b/thesis/own.gls
index ee3ee97..d98eee5 100644
--- a/thesis/own.gls
+++ b/thesis/own.gls
@@ -1,20 +1,82 @@
 \newglossaryentry{iommu}{
     name={IOMMU},
-    description={... desc ...},
+    long={Input/Output Memory Management Unit},
     first={Input/Output Memory Management Unit (IOMMU)},
-    long={Input/Output Memory Management Unit}
+    description={... desc ...}
+}
+
+\newglossaryentry{atc}{
+    name={ATC},
+    long={Address Translation Cache},
+    first={Address Translation Cache (ATC)},
+    description={... desc ...}
 }
 
 \newglossaryentry{bar}{
     name={BAR},
-    description={... desc ...},
+    long={Base Address Register},
     first={Base Address Register (BAR)},
-    long={Base Address Register}
+    description={... desc ...}
 }
 
 \newglossaryentry{dsa}{
     name={DSA},
-    description={... desc ...},
+    long={Intel Data Streaming Accelerator},
     first={Intel Data Streaming Accelerator (DSA)},
-    long={Intel Data Streaming Accelerator}
+    description={... desc ...}
+}
+
+\newglossaryentry{dsa:wq}{
+    name={WQ},
+    long={Work Queue},
+    first={Work Queue (WQ)},
+    description={... desc ...}
+}
+
+\newglossaryentry{dsa:swq}{
+    name={SWQ},
+    long={Shared Work Queue},
+    first={Shared Work Queue (SWQ)},
+    description={... desc ...}
+}
+
+\newglossaryentry{dsa:dwq}{
+    name={DWQ},
+    long={Dedicated Work Queue},
+    first={Dedicated Work Queue (DWQ)},
+    description={... desc ...}
+}
+
+\newglossaryentry{pcie-dmr}{
+    name={PCIe Deferrable Memory Write Request},
+    description={... desc ...}
+}
+
+\newglossaryentry{dsa:engine}{
+    name={Engine},
+    description={... desc ...}
+}
+
+\newglossaryentry{dsa:group}{
+    name={Group},
+    description={... desc ...}
+}
+
+\newglossaryentry{x86:enqcmd}{
+    name={ENQCMD},
+    first={x86 Instruction ENQCMD},
+    description={... desc ...}
+}
+
+\newglossaryentry{x86:movdir64b}{
+    name={MOVDIR64B},
+    first={x86 Instruction MOVDIR64B},
+    description={... desc ...}
+}
+
+\newglossaryentry{x86:pasid}{
+    name={PASID},
+    long={Process Address Space ID},
+    first={Process Address Space ID (PASID)},
+    description={... desc ...}
 }
\ No newline at end of file