4 Commits

  1. BIN
      thesis/bachelor.pdf
  2. 2
      thesis/content/01_disclaimer.tex
  3. 2
      thesis/content/02_abstract.tex
  4. 4
      thesis/own.gls

BIN
thesis/bachelor.pdf

2
thesis/content/01_disclaimer.tex

@ -1,6 +1,6 @@
\section*{\vfill{} \thispagestyle{empty} Statement of Authorship}
I hereby declare that I am the sole author of this master thesis and that I have not used any
I hereby declare that I am the sole author of this bachelor thesis and that I have not used any
sources other than those listed in the bibliography and identified as references. I further
declare that I have not submitted this thesis at any other institution in order to obtain a
degree.

2
thesis/content/02_abstract.tex

@ -8,7 +8,7 @@
% geben (für irgendetwas müssen die Betreuer ja auch noch da
% sein).
This bachelor's thesis explores data locality in heterogeneous memory systems, characterized by advancements in main memory technologies such as Non-Volatile RAM (NVRAM), High Bandwidth Memory (HBM), and Remote Memory. Systems equipped with more than one type of main memory necessitate strategic decisions regarding data placement to take advantage of the properties of the different storage tiers. In response to this challenge, Intel has introduced the Data Streaming Accelerator (DSA), which offloads data operations, offering a potential avenue for enhancing efficiency in data-intensive applications. The primary objective of this thesis is to provide a comprehensive analysis and characterization of the architecture and performance of the DSA, along with its application to a domain-specific prefetching methodology aimed at accelerating database queries within heterogeneous memory systems.
This bachelor's thesis explores data locality in heterogeneous memory systems, characterized by advancements in main memory technologies such as Non-Volatile RAM (NVRAM), High Bandwidth Memory (HBM), and Remote Memory. Systems equipped with more than one type of main memory necessitate strategic decisions regarding data placement to take advantage of the properties of the different storage tiers. In response to this challenge, Intel has introduced the Data Streaming Accelerator (DSA), which offloads data operations, offering a potential avenue for enhancing efficiency in data-intensive applications. The primary objective of this thesis is to provide a comprehensive analysis and characterization of the architecture and performance of the DSA, along with its application to a domain-specific prefetching methodology aimed at accelerating database queries within heterogeneous memory systems. We contribute a versatile implementation of a cache, offloading copy operations to the DSA.
%%% Local Variables:
%%% TeX-master: "diplom"

4
thesis/own.gls

@ -97,8 +97,8 @@
\newglossaryentry{numa}{
short={NUMA},
name={NUMA},
long={Non Uniform Memory Architecture},
first={Non Uniform Memory Architecture (NUMA)},
long={Non-Uniform Memory Architecture},
first={Non-Uniform Memory Architecture (NUMA)},
description={... desc ...}
}

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