This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator

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bachelor-thesis/benchmarks/configuration-files

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Constantin Fürst 10a791dea1 remove the experimental code branches that turned out not to yield any benefit (sched-yield has too high delay and with the new load balancer, subchunking for aggrj is also not needed anymore)		11 months ago
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8n1d1e1w.conf	add dsa configuration files to repository	1 year ago
8n1d4e1w.conf	add dsa configuration files to repository	1 year ago
load-dsaconfig.sh	add script to disable dsa and then load a new config	1 year ago