This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator

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bachelor-thesis/benchmarks/util

History

Constantin Fürst 10a791dea1 remove the experimental code branches that turned out not to yield any benefit (sched-yield has too high delay and with the new load balancer, subchunking for aggrj is also not needed anymore)		11 months ago
..
json@9cca280a4d	restructure of directory layout	1 year ago
barrier.hpp	restructure of directory layout	1 year ago
dml-helper.hpp	fix include naming	1 year ago
task-data.hpp	add peak perf benchmark descriptors	1 year ago