This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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Constantin Fürst 282f7c7736 improve clarity for c5 explanation of why weak wait and access are required, add section labeling to the section containing this paragraph 11 months ago
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perf.svg remeassure performance for out of cache allocation 11 months ago
qdp-xeonmax-prefetch-tca2-tcb1-tcj1-tmul1-wl1073741824-cs8388608.csv restructure evaluation results, add new results with out of cache allocation 11 months ago
qdp-xeonmax-prefetch-tca2-tcb1-tcj1-tmul16-wl4294967296-cs8388608.csv restructure evaluation results, add new results with out of cache allocation 11 months ago
qdp-xeonmax-prefetch-tca2-tcb1-tcj1-tmul16-wl4294967296-cs16777216.csv restructure evaluation results, add new results with out of cache allocation 11 months ago
qdp-xeonmax-prefetch-tca2-tcb1-tcj1-tmul16-wl4294967296-cs33554432.csv restructure evaluation results, add new results with out of cache allocation 11 months ago