This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator

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bachelor-thesis/test-project/binaries

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Constantin Fürst 282f7c7736 improve clarity for c5 explanation of why weak wait and access are required, add section labeling to the section containing this paragraph		11 months ago
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dml-test	add error print output for dml status code	1 year ago
tests	add DML test binaries	1 year ago
tests_mt	add DML test binaries	1 year ago