This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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\newglossaryentry{iommu}{
short={IOMMU},
name={IOMMU},
long={Input/Output Memory Management Unit},
first={Input/Output Memory Management Unit (IOMMU)},
description={\textsc{\glsentrylong{iommu}:} Hardware component responsible for mapping memory addresses for peripheral devices performing Direct Memory Access (DMA). May also provide memory protection mechanisms.}
}
\newglossaryentry{dsa}{
short={DSA},
name={DSA},
long={Intel Data Streaming Accelerator},
first={Intel Data Streaming Accelerator (DSA)},
description={\textsc{\glsentrylong{dsa}:} A component of modern Intel server processors, capable of executing common data operations asynchronously and thereby offloading them from the CPU.}
}
\newglossaryentry{dsa:wq}{
short={WQ},
name={WQ},
long={Work Queue},
first={Work Queue (WQ)},
description={\textsc{\glsentrylong{dsa:wq}:} Architectural component of the \gls{dsa} to which data is submitted by the user. See Section \ref{subsec:state:dsa-arch-comp} for more detail on its function.}
}
\newglossaryentry{dsa:swq}{
short={SWQ},
name={SWQ},
long={Shared Work Queue},
first={Shared Work Queue (SWQ)},
description={\textsc{\glsentrylong{dsa:swq}:} A type of Work Queue to which submissions are implicitly synchronized, allowing safe usage from multiple processes. See Section \ref{subsec:state:dsa-arch-comp} for more detail.}
}
\newglossaryentry{dsa:dwq}{
short={DWQ},
name={DWQ},
long={Dedicated Work Queue},
first={Dedicated Work Queue (DWQ)},
description={\textsc{\glsentrylong{dsa:dwq}:} A type of Work Queue only usable by one process, and therefore with potentially lower submission overhead. See Section \ref{subsec:state:dsa-arch-comp} for more detail.}
}
\newglossaryentry{x86:pasid}{
short={PASID},
name={PASID},
long={Process Address Space ID},
first={Process Address Space ID (PASID)},
description={\textsc{\glsentrylong{x86:pasid}:} Identifier used by the \glsentryshort{dsa} in conjunction with the \glsentryshort{iommu} to resolve virtual addresses. See Section \ref{subsubsec:state:dsa-vaddr}.}
}
\newglossaryentry{intel:dml}{
short={Intel DML},
name={Intel DML},
long={Intel Data Mover Library},
first={Intel Data Mover Library (Intel DML)},
description={\textsc{\glsentrylong{intel:dml}:} A library presenting a high-level interface with the \glsentryshort{dsa}. View the usage example in Section \ref{sec:state:dml} or the library documentation \cite{intel:dmldoc} for further information.}
}
\newglossaryentry{numa}{
short={NUMA},
name={NUMA},
long={Non-Uniform Memory Architecture},
first={Non-Uniform Memory Architecture (NUMA)},
description={\textsc{\glsentrylong{numa}:} Describes a system architecture organized into different Nodes with each node observing different access patterns to memory for the available address range.}
}
\newglossaryentry{numa:node}{
short={Node},
name={Node},
long={NUMA-Node},
first={NUMA-Node (Node)},
description={\textsc{\glsentrylong{numa:node}:} A Node in a NUMA-system. See the Entry for NUMA for an explanation of both.}
}
\newglossaryentry{hbm}{
short={HBM},
name={HBM},
long={High Bandwidth Memory},
first={High Bandwidth Memory (HBM)},
description={\textsc{\glsentrylong{hbm}:} Main memory technology, consisting of stacked DRAM-dies. Section \ref{sec:state:hbm} offers more detail.}
}
\newglossaryentry{dram}{
short={DDR-SDRAM},
name={DDR-SDRAM},
long={Double Data Rate Synchronous Dynamic Random Access Memory},
first={Double Data Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM)},
description={\textsc{\glsentrylong{dram}:} Main memory technology found in common computer systems.}
}
\newglossaryentry{qdp}{
short={QdP},
name={QdP},
long={Query-driven Prefetching},
first={Query-driven Prefetching (QdP)},
description={\textsc{\glsentrylong{qdp}:} Methodology to determine database columns worth prefetching to cache in order to accelerate a queries. Described in Section \ref{sec:state:qdp}.}
}
\newglossaryentry{mempress}{
short={memory pressure},
name={Memory Pressure},
description={\textsc{Memory Pressure:} Situation where high memory utilization is encountered.}
}
\newglossaryentry{api}{
short={API},
name={API},
long={Application Programming Interface},
first={Application Programming Interface (API)},
description={\textsc{\glsentrylong{api}:} Definition of the interface provided by an application, enabling interaction between software components or systems.}
}
\newglossaryentry{nvram}{
short={NVRAM},
name={NVRAM},
long={Non-Volatile RAM},
first={Non-Volatile RAM (NVRAM)},
description={\textsc{\glsentrylong{nvram}:} Main memory technology which, unlike \glsentryshort{dram}, retains data when without power.}
}
\newglossaryentry{mutmet}{
short={mutating method},
name={Mutating Method},
description={\textsc{Mutating Method:} Member function (method) capable of mutating data of a classes instances. This is the default in C++, unless explicitly disabled by marking a method const or static.}
}