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254 lines
8.0 KiB
254 lines
8.0 KiB
#include <iostream>
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#include <random>
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#include <vector>
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#include <string>
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#include <omp.h>
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#include "cache.hpp"
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static constexpr size_t SIZE_64_MIB = 64 * 1024 * 1024;
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dsacache::Cache CACHE;
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void InitCache(const std::string& device) {
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if (device == "default") {
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auto cache_policy = [](const int numa_dst_node, const int numa_src_node, const size_t data_size) {
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return numa_dst_node;
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};
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auto copy_policy = [](const int numa_dst_node, const int numa_src_node, const size_t data_size) {
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return std::vector<int>{ numa_dst_node };
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};
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CACHE.Init(cache_policy,copy_policy);
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}
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else if (device == "xeonmax") {
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auto cache_policy = [](const int numa_dst_node, const int numa_src_node, const size_t data_size) {
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// xeon max is configured to have hbm on node ids that are +8
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return numa_dst_node < 8 ? numa_dst_node + 8 : numa_dst_node;
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};
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auto copy_policy = [](const int numa_dst_node, const int numa_src_node, const size_t data_size) {
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if (data_size < SIZE_64_MIB) {
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// if the data size is small then the copy will just be carried
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// out by the destination node which does not require setting numa
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// thread affinity as the selected dsa engine is already the one
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// present on the calling thread
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return std::vector<int>{ (numa_dst_node >= 8 ? numa_dst_node - 8 : numa_dst_node) };
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}
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else {
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// for sufficiently large data, smart copy is used which will utilize
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// all four engines for intra-socket copy operations and cross copy on
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// the source and destination nodes for inter-socket copy
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const bool same_socket = ((numa_dst_node ^ numa_src_node) & 4) == 0;
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if (same_socket) {
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const bool socket_number = numa_dst_node >> 2;
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if (socket_number == 0) return std::vector<int>{ 0, 1, 2, 3 };
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else return std::vector<int>{ 4, 5, 6, 7 };
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}
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else {
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return std::vector<int>{
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(numa_src_node >= 8 ? numa_src_node - 8 : numa_src_node),
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(numa_dst_node >= 8 ? numa_dst_node - 8 : numa_dst_node)
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};
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}
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}
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};
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CACHE.Init(cache_policy,copy_policy);
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}
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else {
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std::cerr << "Given device '" << device << "' not supported!" << std::endl;
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exit(-1);
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}
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}
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uint8_t* GetRandomArray(const size_t size) {
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uint8_t* array = new uint8_t[size];
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std::uniform_int_distribution<uint8_t> unif(std::numeric_limits<uint8_t>::min(), std::numeric_limits<uint8_t>::max());
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std::default_random_engine re;
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for (size_t i = 0; i < size; i++) {
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array[i] = unif(re);
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}
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return array;
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}
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bool IsEqual(const uint8_t* a, const uint8_t* b, const size_t size) {
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for (size_t i = 0; i < size; i++) {
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try {
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if (a[i] != b[i]) return false;
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}
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catch (...) {
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return false;
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}
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}
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return true;
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}
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std::unique_ptr<dsacache::CacheData> PerformAccessAndTest(uint8_t* src, const size_t size, const int tid) {
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std::unique_ptr<dsacache::CacheData> data_cache = CACHE.Access(
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reinterpret_cast<uint8_t *>(src),
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size * sizeof(uint8_t)
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);
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data_cache->WaitOnCompletion(dsacache::WAIT_WEAK);
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uint8_t* cached_imm = reinterpret_cast<uint8_t *>(data_cache->GetDataLocation());
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// check the value immediately just to see if ram or cache was returned
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if (src == cached_imm) {
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std::cout << "[" << tid << "] Caching did not immediately yield different data location." << std::endl;
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}
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else if (cached_imm == nullptr) {
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std::cout << "[" << tid << "] Immediately got nullptr." << std::endl;
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}
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else {
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std::cout << "[" << tid << "] Immediately got different data location." << std::endl;
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}
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// waits for the completion of the asynchronous caching operation
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data_cache->WaitOnCompletion();
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// gets the cache-data-location from the struct
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uint8_t* cached = reinterpret_cast<uint8_t *>(data_cache->GetDataLocation());
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// tests on the resulting value
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if (src == cached) {
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std::cout << "[" << tid << "] Caching did not affect data location." << std::endl;
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}
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else if (cached == nullptr) {
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std::cerr << "[" << tid << "] Got nullptr from cache." << std::endl;
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}
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else {
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std::cout << "[" << tid << "] Got different data location from cache." << std::endl;
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}
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if (IsEqual(src,cached,size)) {
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std::cout << "[" << tid << "] Cached data is correct." << std::endl;
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}
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else {
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std::cerr << "[" << tid << "] Cached data is wrong." << std::endl;
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}
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return std::move(data_cache);
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}
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void RunTestST(const size_t size) {
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uint8_t* data = GetRandomArray(size);
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static constexpr int tid = 0;
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std::cout << "[" << tid << "] first access --- " << std::endl;
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PerformAccessAndTest(data, size, tid);
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std::cout << "[" << tid << "] second access --- " << std::endl;
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PerformAccessAndTest(data, size, tid);
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std::cout << "[" << tid << "] end of application --- " << std::endl;
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}
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void RunTestMT(const size_t size) {
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uint8_t* data = GetRandomArray(size);
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#pragma omp parallel
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{
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const int tid = omp_get_thread_num();
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std::cout << "[" << tid << "] first access --- " << std::endl;
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PerformAccessAndTest(data, size, tid);
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std::cout << "[" << tid << "] second access --- " << std::endl;
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PerformAccessAndTest(data, size, tid);
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std::cout << "[" << tid << "] end of block --- " << std::endl;
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}
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}
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void RunTestFlush(const size_t size) {
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uint8_t* data1 = GetRandomArray(size);
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uint8_t* data2 = GetRandomArray(size);
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uint8_t* data3 = GetRandomArray(size);
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static constexpr int tid = 0;
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std::cout << "[" << tid << "] first access to data d1 and keepalive --- " << std::endl;
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const auto c1 = PerformAccessAndTest(data1, size, tid);
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std::cout << "[" << tid << "] second access to d2 lets d2 vanish --- " << std::endl;
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PerformAccessAndTest(data2, size, tid);
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std::cout << "[" << tid << "] third access to d3 should clear d2 --- " << std::endl;
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PerformAccessAndTest(data3, size, tid);
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std::cout << "[" << tid << "] end of block and test d1 == cache1 --- " << std::endl;
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if (IsEqual(data1, c1->GetDataLocation(), size)) {
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std::cout << "[" << tid << "] Cached d1 is still correct." << std::endl;
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}
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else {
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std::cerr << "[" << tid << "] Cached d1 is bad." << std::endl;
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}
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}
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int main(int argc, char **argv) {
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if (argc != 4) {
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std::cerr << "This application requires three parameters!" << std::endl;
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std::cout << "Please provide the following positional arguments: [device] [mode] [size]" << std::endl;
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std::cout << "[device] from { default, xeonmax } which influences cache and execution placement" << std::endl;
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std::cout << "[mode] from { st, mt, flt } or single and multi threaded and flushtest respectively" << std::endl;
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std::cout << "[size] positive integral number, amount of bytes in data array" << std::endl;
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std::cout << "for flushtest the given size should be 1/3 of the available cache size" << std::endl;
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exit(-1);
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}
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const std::string device = argv[1];
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const std::string mode = argv[2];
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const std::string size_s = argv[3];
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uint32_t size = 0;
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try {
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size = std::stoul(size_s);
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}
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catch (...) {
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std::cerr << "Given Size '" << size_s << "' caused error during conversion to number!" << std::endl;
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}
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InitCache(device);
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if (mode == "st") {
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RunTestST(size);
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}
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else if (mode == "mt") {
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RunTestMT(size);
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}
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else if (mode == "flt") {
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RunTestFlush(size);
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}
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else {
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std::cerr << "Given Mode '" << mode << "' not supported!" << std::endl;
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exit(-1);
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}
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}
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