This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator

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bachelor-thesis/thesis/checkbiw

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Constantin Fürst a4dac61730 change config to allow 64 threads for stage 1 and 32 for stage 2 in all benchmarks		11 months ago
..
contrib/diction	add thesis template	1 year ago
doc	add checkibw makefile	12 months ago
src	add thesis template	1 year ago
COPYING	add thesis template	1 year ago
MAINTAINER	add thesis template	1 year ago
TODO	add thesis template	1 year ago