This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator

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Constantin Fürst a4dac61730 change config to allow 64 threads for stage 1 and 32 for stage 2 in all benchmarks		11 months ago
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build.nix	add thesis template	1 year ago
release.nix	add thesis template	1 year ago
sources.json	add thesis template	1 year ago
sources.nix	add thesis template	1 year ago
tex-toolchain.nix	add thesis template	1 year ago