This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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  1. \begin{tabular}{ll}
  2. \toprule
  3. Configuration & Raw Time \\
  4. \midrule
  5. DDR-SDRAM (Baseline) & 131.18 ms \\
  6. HBM (Upper Limit) & 93.09 ms \\
  7. \bottomrule
  8. \end{tabular}