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This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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bachelor-thesis/thesis/tables/table-qdp-baseline.tex

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\begin{tabular}{ll}
\toprule
Configuration & Raw Time \\
\midrule
DDR-SDRAM (Baseline) & 131.18 ms \\
HBM (Upper Limit) & 93.09 ms \\
\bottomrule
\end{tabular}