This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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  1. \newglossaryentry{iommu}{
  2. short={IOMMU},
  3. name={IOMMU},
  4. long={Input/Output Memory Management Unit},
  5. first={Input/Output Memory Management Unit (IOMMU)},
  6. description={\textsc{\glsentrylong{iommu}:} \todo{write iomu description}}
  7. }
  8. \newglossaryentry{atc}{
  9. short={ATC},
  10. name={ATC},
  11. long={Address Translation Cache},
  12. first={Address Translation Cache (ATC)},
  13. description={\textsc{\glsentrylong{atc}:} \todo{write arc description}}
  14. }
  15. \newglossaryentry{bar}{
  16. short={BAR},
  17. name={BAR},
  18. long={Base Address Register},
  19. first={Base Address Register (BAR)},
  20. description={\textsc{\glsentrylong{bar}:} \todo{write bar description}}
  21. }
  22. \newglossaryentry{dsa}{
  23. short={DSA},
  24. name={DSA},
  25. long={Intel Data Streaming Accelerator},
  26. first={Intel Data Streaming Accelerator (DSA)},
  27. description={\textsc{\glsentrylong{dsa}:} A component of modern Intel server processors, capable of executing common data operations asynchronously and thereby offloading them from the CPU.}
  28. }
  29. \newglossaryentry{dsa:wq}{
  30. short={WQ},
  31. name={WQ},
  32. long={Work Queue},
  33. first={Work Queue (WQ)},
  34. description={\textsc{\glsentrylong{dsa:wq}:} Architectural component of the \gls{dsa} to which data is submitted by the user. See Section \ref{subsec:state:dsa-arch-comp} for more detail on its function.}
  35. }
  36. \newglossaryentry{dsa:swq}{
  37. short={SWQ},
  38. name={SWQ},
  39. long={Shared Work Queue},
  40. first={Shared Work Queue (SWQ)},
  41. description={\textsc{\glsentrylong{dsa:swq}:} A type of Work Queue to which submissions are implicitly synchronized, allowing safe usage from multiple processes. See Section \ref{subsec:state:dsa-arch-comp} for more detail.}
  42. }
  43. \newglossaryentry{dsa:dwq}{
  44. short={DWQ},
  45. name={DWQ},
  46. long={Dedicated Work Queue},
  47. first={Dedicated Work Queue (DWQ)},
  48. description={\textsc{\glsentrylong{dsa:dwq}:} A type of Work Queue only usable by one process, and therefore with potentially lower submission overhead. See Section \ref{subsec:state:dsa-arch-comp} for more detail.}
  49. }
  50. \newglossaryentry{pcie-dmr}{
  51. short={DMR},
  52. name={DMR},
  53. long={PCIe Deferrable Memory Write Request},
  54. first={PCIe Deferrable Memory Write Request (DMR)},
  55. description={\textsc{\glsentrylong{pcie-dmr}:} \todo{write pcie-dmr description}}
  56. }
  57. \newglossaryentry{x86:enqcmd}{
  58. short={ENQCMD},
  59. name={ENQCMD},
  60. long={x86 Instruction ENQCMD},
  61. first={x86 Instruction ENQCMD},
  62. description={\textsc{\glsentrylong{x86:enqcmd}:} \todo{write enqcmd description}}
  63. }
  64. \newglossaryentry{x86:movdir64b}{
  65. short={MOVDIR64B},
  66. name={MOVDIR64B},
  67. long={x86 Instruction MOVDIR64B},
  68. first={x86 Instruction MOVDIR64B},
  69. description={\textsc{\glsentrylong{x86:movdir64b}:} \todo{write movdir64b description}}
  70. }
  71. \newglossaryentry{x86:pasid}{
  72. short={PASID},
  73. name={PASID},
  74. long={Process Address Space ID},
  75. first={Process Address Space ID (PASID)},
  76. description={\textsc{\glsentrylong{x86:pasid}:} Identifier used by the \glsentryshort{dsa} in conjunction with the \glsentryshort{iommu} to resolve virtual addresses. See Section \ref{subsubsec:state:dsa-vaddr}.}
  77. }
  78. \newglossaryentry{intel:dml}{
  79. short={Intel DML},
  80. name={Intel DML},
  81. long={Intel Data Mover Library},
  82. first={Intel Data Mover Library (Intel DML)},
  83. description={\textsc{\glsentrylong{intel:dml}:} A library presenting a high-level interface with the \glsentryshort{dsa}. View the usage example in Section \ref{sec:state:dml} or the library documentation \cite{intel:dmldoc} for further information.}
  84. }
  85. \newglossaryentry{numa}{
  86. short={NUMA},
  87. name={NUMA},
  88. long={Non-Uniform Memory Architecture},
  89. first={Non-Uniform Memory Architecture (NUMA)},
  90. description={\textsc{\glsentrylong{numa}:} Describes a system architecture organized into different Nodes with each node observing different access patterns to memory for the available address range.}
  91. }
  92. \newglossaryentry{numa:node}{
  93. short={Node},
  94. name={Node},
  95. long={NUMA-Node},
  96. first={NUMA-Node (Node)},
  97. description={\textsc{\glsentrylong{numa:node}:} A Node in a NUMA-system. See the Entry for NUMA for an explanation of both.}
  98. }
  99. \newglossaryentry{hbm}{
  100. short={HBM},
  101. name={HBM},
  102. long={High Bandwidth Memory},
  103. first={High Bandwidth Memory (HBM)},
  104. description={\textsc{\glsentrylong{hbm}:} Main memory technology, consisting of stacked DRAM-dies. Section \ref{sec:state:hbm} offers more detail.}
  105. }
  106. \newglossaryentry{dram}{
  107. short={DDR-SDRAM},
  108. name={DDR-SDRAM},
  109. long={Double Data Rate Synchronous Dynamic Random Access Memory},
  110. first={Double Data Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM)},
  111. description={\textsc{\glsentrylong{dram}:} Main memory technology found in common computer systems.}
  112. }
  113. \newglossaryentry{qdp}{
  114. short={QdP},
  115. name={QdP},
  116. long={Query-driven Prefetching},
  117. first={Query-driven Prefetching (QdP)},
  118. description={\textsc{\glsentrylong{qdp}:} Methodology to determine database columns worth prefetching to cache in order to accelerate a queries. Described in Section \ref{sec:state:qdp}.}
  119. }
  120. \newglossaryentry{mempress}{
  121. short={memory pressure},
  122. name={Memory Pressure},
  123. long={Memory Pressure},
  124. description={\textsc{\glsentrylong{mempress}:} Situation where high memory utilization is encountered.}
  125. }
  126. \newglossaryentry{api}{
  127. short={API},
  128. name={API},
  129. long={Application Programming Interface},
  130. first={Application Programming Interface (API)},
  131. description={\textsc{\glsentrylong{api}:} Public functions exposed by a library, through which programs utilizing this library can interact with it.}
  132. }
  133. \newglossaryentry{remotemem}{
  134. short={Remote Memory},
  135. name={Remote Memory},
  136. long={Remote Memory},
  137. description={\textsc{\glsentrylong{remotemem}:} ... desc ... \todo{write remotemem description}}
  138. }
  139. \newglossaryentry{nvram}{
  140. short={NVRAM},
  141. name={NVRAM},
  142. long={Non-Volatile RAM},
  143. first={Non-Volatile RAM (NVRAM)},
  144. description={\textsc{\glsentrylong{nvram}:} Main memory technology which, unlike \glsentryshort{dram}, retains data when without power.}
  145. }