This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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  1. \newglossaryentry{iommu}{
  2. short={IOMMU},
  3. name={IOMMU},
  4. long={Input/Output Memory Management Unit},
  5. first={Input/Output Memory Management Unit (IOMMU)},
  6. description={\textsc{\glsentrylong{iommu}:} \todo{write iomu description}}
  7. }
  8. \newglossaryentry{dsa}{
  9. short={DSA},
  10. name={DSA},
  11. long={Intel Data Streaming Accelerator},
  12. first={Intel Data Streaming Accelerator (DSA)},
  13. description={\textsc{\glsentrylong{dsa}:} A component of modern Intel server processors, capable of executing common data operations asynchronously and thereby offloading them from the CPU.}
  14. }
  15. \newglossaryentry{dsa:wq}{
  16. short={WQ},
  17. name={WQ},
  18. long={Work Queue},
  19. first={Work Queue (WQ)},
  20. description={\textsc{\glsentrylong{dsa:wq}:} Architectural component of the \gls{dsa} to which data is submitted by the user. See Section \ref{subsec:state:dsa-arch-comp} for more detail on its function.}
  21. }
  22. \newglossaryentry{dsa:swq}{
  23. short={SWQ},
  24. name={SWQ},
  25. long={Shared Work Queue},
  26. first={Shared Work Queue (SWQ)},
  27. description={\textsc{\glsentrylong{dsa:swq}:} A type of Work Queue to which submissions are implicitly synchronized, allowing safe usage from multiple processes. See Section \ref{subsec:state:dsa-arch-comp} for more detail.}
  28. }
  29. \newglossaryentry{dsa:dwq}{
  30. short={DWQ},
  31. name={DWQ},
  32. long={Dedicated Work Queue},
  33. first={Dedicated Work Queue (DWQ)},
  34. description={\textsc{\glsentrylong{dsa:dwq}:} A type of Work Queue only usable by one process, and therefore with potentially lower submission overhead. See Section \ref{subsec:state:dsa-arch-comp} for more detail.}
  35. }
  36. \newglossaryentry{x86:pasid}{
  37. short={PASID},
  38. name={PASID},
  39. long={Process Address Space ID},
  40. first={Process Address Space ID (PASID)},
  41. description={\textsc{\glsentrylong{x86:pasid}:} Identifier used by the \glsentryshort{dsa} in conjunction with the \glsentryshort{iommu} to resolve virtual addresses. See Section \ref{subsubsec:state:dsa-vaddr}.}
  42. }
  43. \newglossaryentry{intel:dml}{
  44. short={Intel DML},
  45. name={Intel DML},
  46. long={Intel Data Mover Library},
  47. first={Intel Data Mover Library (Intel DML)},
  48. description={\textsc{\glsentrylong{intel:dml}:} A library presenting a high-level interface with the \glsentryshort{dsa}. View the usage example in Section \ref{sec:state:dml} or the library documentation \cite{intel:dmldoc} for further information.}
  49. }
  50. \newglossaryentry{numa}{
  51. short={NUMA},
  52. name={NUMA},
  53. long={Non-Uniform Memory Architecture},
  54. first={Non-Uniform Memory Architecture (NUMA)},
  55. description={\textsc{\glsentrylong{numa}:} Describes a system architecture organized into different Nodes with each node observing different access patterns to memory for the available address range.}
  56. }
  57. \newglossaryentry{numa:node}{
  58. short={Node},
  59. name={Node},
  60. long={NUMA-Node},
  61. first={NUMA-Node (Node)},
  62. description={\textsc{\glsentrylong{numa:node}:} A Node in a NUMA-system. See the Entry for NUMA for an explanation of both.}
  63. }
  64. \newglossaryentry{hbm}{
  65. short={HBM},
  66. name={HBM},
  67. long={High Bandwidth Memory},
  68. first={High Bandwidth Memory (HBM)},
  69. description={\textsc{\glsentrylong{hbm}:} Main memory technology, consisting of stacked DRAM-dies. Section \ref{sec:state:hbm} offers more detail.}
  70. }
  71. \newglossaryentry{dram}{
  72. short={DDR-SDRAM},
  73. name={DDR-SDRAM},
  74. long={Double Data Rate Synchronous Dynamic Random Access Memory},
  75. first={Double Data Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM)},
  76. description={\textsc{\glsentrylong{dram}:} Main memory technology found in common computer systems.}
  77. }
  78. \newglossaryentry{qdp}{
  79. short={QdP},
  80. name={QdP},
  81. long={Query-driven Prefetching},
  82. first={Query-driven Prefetching (QdP)},
  83. description={\textsc{\glsentrylong{qdp}:} Methodology to determine database columns worth prefetching to cache in order to accelerate a queries. Described in Section \ref{sec:state:qdp}.}
  84. }
  85. \newglossaryentry{mempress}{
  86. short={memory pressure},
  87. name={Memory Pressure},
  88. long={Memory Pressure},
  89. description={\textsc{\glsentrylong{mempress}:} Situation where high memory utilization is encountered.}
  90. }
  91. \newglossaryentry{api}{
  92. short={API},
  93. name={API},
  94. long={Application Programming Interface},
  95. first={Application Programming Interface (API)},
  96. description={\textsc{\glsentrylong{api}:} Definition of the interface provided by an application, enabling interaction between software components or systems.}
  97. }
  98. \newglossaryentry{nvram}{
  99. short={NVRAM},
  100. name={NVRAM},
  101. long={Non-Volatile RAM},
  102. first={Non-Volatile RAM (NVRAM)},
  103. description={\textsc{\glsentrylong{nvram}:} Main memory technology which, unlike \glsentryshort{dram}, retains data when without power.}
  104. }