This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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\begin{tabular}{llll}
\toprule
Configuration & Speedup & Cache Hitrate & Raw Time \\
\midrule
DDR-SDRAM (Baseline) & x1.00 & \textemdash & 131.18 ms \\
HBM (Upper Limit) & x1.41 & \textemdash & 93.09 ms \\
Prefetching & x0.82 & 89.38 \% & 159.72 ms \\
Prefetching, Distributed Columns & x1.23 & 93.20 \% & 106.52 ms \\
\bottomrule
\end{tabular}