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This contains my bachelors thesis and associated tex files, code snippets and maybe more. Topic: Data Movement in Heterogeneous Memories with Intel Data Streaming Accelerator
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Constantin Fürst 6d9002d1e7
use different engine configuration depending on whether intra socket (all 4 engines on the socket) or inter socket (src and destination engine, cross copy) is the copy type 		1 year ago
benchmarks use different engine configuration depending on whether intra socket (all 4 engines on the socket) or inter socket (src and destination engine, cross copy) is the copy type 1 year ago
test-project add error print output for dml status code 1 year ago
thesis fix missing detail on the first processor with dsa, add todos and clear the bullet points of stuff that has already been added to the text - all in technical background chapter 1 year ago
.gitignore add tex makefile to the project 1 year ago
.gitmodules restructure of directory layout 1 year ago
README.md Initial commit 1 year ago

README.md

bachelor-thesis